1 Tuning Algorithm Overview

The read tuning algorithm is recommended by the SD Group and JEDEC Solid State Technology Association to compensate for timing variations due to a collection of system factors above 50 MHz high speed of operation. These factors include changes in silicon processes, operating temperature and voltage, PCB loading, as well as SD and eMMC slave device output timing.

During the read tuning process, the CLK-DAT latching position is adjusted through the delay module in single steps increments across a full range of 32 ratio elements. This adjustment can be done via automatic hardware tuning or manual software tuning. Limitations exist with the hardware tuning mechanism so the software tuning mechanism is the preferred method of implementation. This application report briefly describes the hardware tuning mechanism limitation and then goes over the software tuning algorithm in detail.