SPRACU1A October 2020 – June 2021 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6441 , AM6442
High-speed (HS) bypass capacitors are critical for proper DDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors to VDDS_DDR and the associated ground connections. Table 1-3 contains the specification for the HS bypass capacitors and for the power connections on the PCB. Generally speaking, TI recommends:
For any additional SDRAM requirements, see the manufacturer's data sheet.
Number | Parameter | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
1 | HS bypass capacitor package size (1) | 0201 | 0402 | 10 Mils | |
2 | Distance, HS bypass capacitor to processor being bypassed (2)(3)(4) | 400 | Mils | ||
3 | Processor HS bypass capacitor count per VDDS_DDR rail | See PDN Guide (9) | Devices | ||
4 | Processor HS bypass capacitor total capacitance per VDDS_DDR rail | See PDN Guide (9) | µF | ||
5 | Number of connection vias for each device power/ground ball | 1 | Vias | ||
6 | Trace length from processor power/ground ball to connection via (2) | 35 | 70 | Mils | |
7 | Distance, HS bypass capacitor to DDR device being bypassed (5) | 150 | Mils | ||
8 | DDR device HS bypass capacitor count(6) | 12 | Devices | ||
9 | DDR device HS bypass capacitor total capacitance (6) | 0.85 | µF | ||
10 | Number of connection vias for each HS capacitor (7)(8) | 2 | Vias | ||
11 | Trace length from bypass capacitor to connection via (2)(8) | 35 | 100 | Mils | |
12 | Number of connection vias for each DDR device power/ground ball | 1 | Vias | ||
13 | Trace length from DDR device power/ground ball to connection via (2)(2) | 35 | 60 | Mils |