SPRAD96B November   2023  – January 2024 AM62P , AM62P-Q1

 

  1.   1
  2.   Trademarks
  3. 1 Introduction
  4. 2 Via Channel Arrays
  5. 3 Width/Spacing Proposal for Escapes
  6. 4 Stackup
  7. 5 Via Sharing
  8. 6 Floorplan Component Placement
  9. 7 Critical Interfaces Impact Placement
  10. 8 Routing Priority
  11. 9 SerDes Interfaces
  12. 10DDR Interfaces
  13. 11Power Decoupling
  14. 12Route Lowest Priority Interfaces Last
  15. 13Summary
  16. 14Revision History

13 Summary

The via channels have been carefully co-designed to ensure escapes for all signals and power while meeting the respective signal and power integrity goals for each interface.

A picture with AM62Px with all signals and power escaped is shown in Figure 13-1.

GUID-6C31E42F-8893-474D-AC2E-DA7F951A33EC-low.png Figure 13-1 AM62Px with Complete Signal and Power Escapes