To reduce the power consumption of the Radar device, the following optimizations can be done:

1. Clock gating of unused modules: This method comes under static clock gating technique. The device includes several peripherals and modules, and several instances. Depending on the application, some of these can be active while others remain unused. The unused peripherals can be clock-gated to save power. In the SDK power measurement example (mmwave_mcuplus_sdk\ti\demo\awr294x\power_measurement), the following are the unused peripherals which have been clock gated:
   1. MSS: SPIA , I2C, MII100, MII10CSIRX, OBSCLKOUT, PMICCLKOUT, TRCCLKOUT
   2. DSS: RTIB, SCIA, CBUFF
   3. RSS: CSI2A
      Figure 6-3 Example Snippet From Power Measurement Demo
2. Dynamic Clock Gating: This type of clock gating can be implemented in two ways, as shown below:
   1. Clock gating using the WFI instruction: the clock gating of the processing core can be done by the invocation of WFI instruction. The applicable cores are MSS ARM Cortex R5F, HSM ARM Cortex M4F and DSS ARM Cortex C66X. The HW-based clock gating of the logic is supported, and any interrupt ungates the logic and wakes up the core.
   2. Explicit clock gating: the modules explicit clock gating can be done using a control processing core.

      For example, the SDK power measurement example ((mmwave_mcuplus_sdk\ti\demo\awr294x\power_measurement)) demonstrates the dynamic clock gating of the hardware accelerator. This enables the capability to clock gate the 4 radar accelerator core IPs (FFT datapath, CFAR, memory compression, local maxima) based on the paramset being executed.

      The example also demonstrates the clock gating of HWA after the frame processing. The HWA is clock-gated once the angle of arrival frame processing is done. The clock is ungated in the frame start ISR.

      
      Figure 6-4 Example Snippets From Power Measurement Demo
   
   
   
3. Dynamic Frequency Scaling: the power measurement example in the SDK (mmwave_mcuplus_sdk\ti\demo\awr294x\power_measurement), demonstrates the dynamic frequency scaling for both DSS and RSS/BSS. The main objective is to lower the frequency during a specific period of time when the higher frequencies are not needed.
   1. DSS dynamic frequency scaling: in Radar devices, the DSS subsystem is mainly used for the computations. Typically, the DSP computations for one measurement cycle gets completed before the computations for the next measurement cycle start. If DSP runs on the same frequency throughout the processing, then DSP results in more power consumption. A better way to optimize is to adjust the frequency during the intermittent time.

      In intermittent time, the DSP clock rate can be reduced from the normal rates to the XTAL frequency (40MHz) to keep the DSP clock rate active and responsive to interrupts, while saving power.

      There are two ways to lower the frequency:

      1. By modifying the clock divider value.
      2. By switching the clock source to a lower frequency.

      For example, in the power measurement example present in the SDK, the DSP clock is switched to the XTAL clock after the DSS Loading time elapses.

      
      
   2. BSS dynamic frequency scaling: for this type of frequency scaling, the TI Firmware supports dynamic frequency scaling by enabling the BSS Underclocking feature. This feature requires the following actions:
      1. First, the necessary clock configurations of the RSS clock and FRC clock sources need to be done.
      2. Reserve MSS RTIC for BSS use for maintaining ticks across the modes.
      3. Handle the functional safety aspects of FRC and WDT.
      4. This can be achieved by performing a Logical monitoring of the Frame timing in the application.
      5. Enable the feature and necessary configurations before unhalting the BSS core.

      For example, in the power measurement present in the SDK (mmwave_mcuplus_sdk\ti\demo\awr294x\power_measurement), the BSS clock source switches to the XTAL (40MHz) clock when the core is idle. This feature cannot be configured through CLI since the feature is enabled in the SBL. Refer to SOC_rcmPopulateBSSControl API in mcu_plus_sdk_awr294x_<ver>.c to enable or disable the BSS Dynamic clocking feature. The 3rd bit of RSS_CR4_BOOT_INFO_REG5 is set to 1 to enable Dynamic clocking. The bit needs to be set to 0 for disabling the feature. MSS RTIC is used by the BSS when the Dynamic clocking feature is enabled.

      Figure 6-5 Example Snippet From Power Measurement Demo
   
   
   
4. Dynamic Power Gating: the power measurement example in the SDK (mmwave_mcuplus_sdk\ti\demo\awr294x\power_measurement), demonstrates the different ways in which power gating can be done. Some of the examples are shown below.
   1. Dynamic power gating of the HWA module: in the device, there is a dedicated power switch available for the HWA module, for which the HWA power supply can be gated off.

      In comparison with the dynamic under-clocking explained earlier, dynamic power-gating needs a reconfiguration of the HWA and consumes more state-transition time (a few micro-seconds more), but provides more power saving.

      For example, HWA is powered down after the AoA frame processing is completed. Hence, HWA needs to be powered up and reconfigured before the next frame start interrupt. In the provided example, this feature works in conjunction with DSS Power Gate. The DSP wakes up, powers up HWA and reconfigures HWA.

      
      
   2. Dynamic power gating of the DSP core: in addition to dynamic under-clocking as explained earlier, the power supply of the DSP can be gated off using a power switch dedicated to the DSP core. In comparison with the dynamic under-clocking explained earlier, dynamic power-gating needs more sophisticated implementation, consumes more state-transition time (a few micro-seconds more), but provides additional power saving.
      Note:

      The contents of the L1 memory are not retained when powered down. Hence, TI recommend to use the L1 memories as a cache and writeback the dirty lines before powering down the DSP. The L2 memory contents are retained.

      For example, the power measurement example provided in the SDK, demonstrates the power gating of the DSP core. DSP is power gated after the DSS loading time is elapsed. DSP is powered up by MSS once the DSP receives the interrupt from the RTIB timer. This timer is configured according to the wakeup time given by the user through CLI. Please make sure the DSP is powered up before the next frame start.

      Note: DSS starts execution from the reset vector when DSS is powered up.
      Note: DSP Gating concerns:

      1. An observation is that in typical use cases for long DSP idle periods (> 8ms), DSP powering down gives benefits over dynamic frequency scaling.
      2. The savings is a function of the save-restore routines as these routines keep the DSP in active mode additionally.
      3. TI recommends to lower the overall device power consumption in thermal shutdown situations.
   
   
5. Transmitters and receivers: the dynamic power saving option can be enabled during the inter chirp idle time to save power. This is done by turning off various circuits. For example, the TX, RX, LO Distribution blocks. The RF, analog sections can be switched OFF between chirps if there is sufficient inter-chirp idle time to save power.
   
6. APLL and FMCW Synthesizer: the APLL supplies the clock to the RX ADCs and the FMCW synthesizer. The FMCW synthesizer generates the chirp waveform supplied to the TX and RX circuits. These circuits need to be ON during chirps and bursts in a frame. In AWR2944, the APLL and FMCW synthesizer can be switched OFF in interburst and interframe times to conserve power.
   
7. RX ADC Low Power Mode: the RX ADC and IFA can operate in two modes: regular and low power ADC mode, which is configurable based on the use case. The low power mode is natively supported for lower sampling rates. If the user's RX sampling rate requirement is low (<7.5MHz IF Bandwidth), then the low power mode can be enabled to conserve power by lowering the operation clock frequency.
   
8. RF Monitors: this method can be used in conserving the monitoring power. The front-end monitors of the device use TXs and RXs to monitor each other with an RF loopback. The set of RXs to be used during RF loopback-based TX monitors is configurable along with other monitoring parameters. This is true for inter-TX mismatch monitors, and phase shifter monitors. Enabling only a single RX can be sufficient to monitor the TXs while also conserving power in comparison with enabling all RXs.