SPRADM7 March 2025 AWR2944 , IWR2944
Figure 5-1 Basic Power Optimization
StrategiesFollowing are the main techniques that can be used for power optimization as shown in the above fig –
In static clock gating, the clock to the unused modules, peripherals, and blocks has been disabled. In dynamic clock gating, the disabling or gating of the clock is being done for a specific duration. After that period of time, the clock can be restored to the previous state.
In static frequency scaling, the frequency of a specific block or module is reduced based on the use case. In dynamic frequency scaling, the frequency of a specific module can be controlled for a particular duration and after that the frequency can be restored to the previous state.
In static power gating, the current has been cut off from the unused blocks or memories depending on the use case. In the dynamic power gating, the supply of current can be controlled for a specific duration for a particular module. After that period of time, the previous state can be restored.