SPRUJ40C may   2022  – may 2023

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1EVM Revisions and Assembly Variants
  5. 2System Description
    1. 2.1 Key Features
      1. 2.1.1 Thermal Compliance
      2. 2.1.2 Processor
      3. 2.1.3 Power Supply
      4. 2.1.4 Memory
      5. 2.1.5 JTAG/Emulator
      6. 2.1.6 Supported Interfaces and Peripherals
      7. 2.1.7 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
    2. 2.2 Functional Block Diagram (SK-AM62 and SK-AM62B)
    3. 2.3 Functional Block Diagram (SK-AM62-P1 and SK-AM62B-P1)
    4. 2.4 AM62x SKEVM Interface Mapping
    5. 2.5 Power ON/OFF Procedures
      1. 2.5.1 Power-On Procedure
      2. 2.5.2 Power-Off Procedure
      3. 2.5.3 Power Test Points
    6. 2.6 Peripheral and Major Component Description
      1. 2.6.1  Clocking
        1. 2.6.1.1 Peripheral Ref Clock
      2. 2.6.2  Reset
      3. 2.6.3  OLDI Display Interface
      4. 2.6.4  CSI Interface
      5. 2.6.5  Audio Codec Interface
      6. 2.6.6  HDMI Display Interface
      7. 2.6.7  JTAG Interface
      8. 2.6.8  Test Automation Header
      9. 2.6.9  UART Interface
      10. 2.6.10 USB Interface
        1. 2.6.10.1 USB 2.0 Type A Interface
        2. 2.6.10.2 USB 2.0 Type C Interface
      11. 2.6.11 Memory Interfaces
        1. 2.6.11.1 DDR4 Interface
        2. 2.6.11.2 OSPI Interface
        3. 2.6.11.3 MMC Interfaces
          1. 2.6.11.3.1 MMC0 - eMMC Interface
          2. 2.6.11.3.2 MMC1 - Micro SD Interface
          3. 2.6.11.3.3 MMC2 - Wilink Interface
        4. 2.6.11.4 EEPROM
      12. 2.6.12 Ethernet Interface
        1. 2.6.12.1 CPSW Ethernet PHY 2 Default Configuration
        2. 2.6.12.2 CPSW Ethernet PHY 1 Default Configuration
      13. 2.6.13 GPIO Port Expander
      14. 2.6.14 GPIO Mapping
      15. 2.6.15 Power
        1. 2.6.15.1 Power Requirements
        2. 2.6.15.2 Power Input
        3. 2.6.15.3 Power Supply
        4. 2.6.15.4 Power Sequencing
        5. 2.6.15.5 AM62x SoC Power
        6. 2.6.15.6 Current Monitoring
      16. 2.6.16 AM62x SKEVM User Setup/Configuration
        1. 2.6.16.1 EVM DIP Switches
        2. 2.6.16.2 Boot Modes
        3. 2.6.16.3 User Test LEDs
      17. 2.6.17 Expansion Headers
        1. 2.6.17.1 PRU Connector
        2. 2.6.17.2 User Expansion Connector
        3. 2.6.17.3 MCU Connector
      18. 2.6.18 Interrupt
      19. 2.6.19 I2C Address Mapping
  6. 3Known Issues and Modifications
    1. 3.1  Issue 1 - HDMI/DSS Incorrect Colors on E1
    2. 3.2  Issue 2 - J9 and J10 Header Alignment on E1
    3. 3.3  Issue 3 - USB Boot descoped on E1
    4. 3.4  Issue 4 - OLDI Connector Orientation and Pinout
    5. 3.5  Issue 5 - Bluetooth descoped on E2 EVMs
    6. 3.6  Issue 6 - Ethernet PHY CLK Skew Default Strapping Changes
    7. 3.7  Issue 7 - TEST_POWERDOWN changes
    8. 3.8  Issue 8 - MMC1_SDCD spurious interrupts
    9. 3.9  Issue 9 - PD Controller I2C2 IRQ Not Pinned Out
    10. 3.10 Issue 10 - INA Current Monitor Adress Changes
    11. 3.11 Issue 11 - Test Automation I2C Buffer Changes
  7.   Regulatory Compliance
  8.   Revision History

2.6.3 OLDI Display Interface

The OLDI0 Display interface of the AM62x SoC is connected to a 40 pin LVDS display connector (J21) Mfr Part# FFC2A32-40-T from GCT. The OLDI Interface supports dual channel 8 bit LVDS output.The pinout and connector orientation is common between E1 and E2 boards but differs from the future 'final' E3 boards. Adapters are available to update the E1/E2 wiring to E3. Do not attempt to connect a display designed for E3 EVMs to the E1/E2 EVM without this adapter.

The Pin-out details of the Display connector are given in Table 2-5.

Table 2-4 Display Connector Pinout (As used by display and the E3 EVM)
Pin no. Signal Pin no. Signal
1 VCC_3V3_SYS(EEPROM_VDD) 21 CH1_LVDS_A2P
2 SoC_I2C0_SCL 22 GND
3 SoC_I2C0_SDA 23 CH1_LVDS_A3N
4 NC 24 CH1_LVDS_A3P
5 NC 25 GND
6 GND 26 CH1_LVDS_A0N
7 GND 27 CH2_LVDS_A0P
8 OLDI_RESETn 28 GND
9 TS_INT# 29 CH2_LVDS_A1N
10 GND 30 CH2_LVDS_A1P
11 CH1_LVDS_A0N 31 GND
12 CH1_LVDS_A0P 32 CH2_LVDS_CLKN
13 GND 33 CH2_LVDS_CLKP
14 CH1_LVDS_A1N 34 GND
15 CH1_LVDS_A1P 35 CH2_LVDS_A2N
16 GND 36 CH2_LVDS_A2P
17 CH1_LVDS_CLKN 37 GND
18 CH1_LVDS_CLKP 38 CH2_LVDS_A3N
19 GND 39 CH2_LVDS_A3P
20 CH1_LVDS_A2N 40 GND
Table 2-5 Display Connector Pinout (E1/E2)
Pin no. Signal Pin no. Signal
40 VCC_3V3_SYS(EEPROM_VDD) 20 CH1_LVDS_A2P
39 GND 19 GND
38 SoC_I2C0_SCL 18 GND
37 SoC_I2C0_SDA 17 CH1_LVDS_A3N
36 NC 16 CH2_LVDS_A0N
35 NC 15 CH1_LVDS_A3P
34 NC 14 CH2_LVDS_A0P
33 TS_INT 13 GND
32 TS_RST 12 GND
31 GND 11 CH2_LVDS_A1N
30 GND 10 CH2_LVDS_CLKN
29 CH1_LVDS_A0N 9 CH2_LVDS_A1P
28 CH1_LVDS_A1N 8 CH2_LVDS_CLKP
27 CH1_LVDS_A0P 7 GND
26 CH1_LVDS_A1P 6 GND
25 GND 5 CH2_LVDS_A2N
24 GND 4 CH2_LVDS_A3N
23 CH1_LVDS_CLKN 3 CH2_LVDS_A2P
22 CH1_LVDS_A2N 2 CH2_LVDS_A3P
21 CH1_LVDS_CLKP 1 GND