SPRUJ55 User guide

SPRUJ55D September 2023 – July 2025 AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

7.5.3.2.2.1.5 Automatic Gain and Phase Correction

Ideally the external Resolver's sine and cosine coils need to have a 90° phase shift. They are also expected to have identical gains. Due to misalignment of the coils during resolver manufacturing, and impedance mismatch on the signal paths to the RDC, gains and phase of Sine and Cosine signals may not match, yielding to an error in angle detection. The RDC can correct those gains and phase errors after observing multiple rotations of the Resolver shaft. The timing of Auto Gain and Phase correction are depicted in Figure 7-158:

Step 1: Excitation frequency is generated, incoming DC offset is cancelled by averaging the sin and cos signals over multiple excitation signal periods and correcting for the deviation from ideal mid-point (or bandpass filter needs to be enabled). Ideal sample time is selected, and RDC starts generating angle data. For this loop to work correctly, resolver shaft needs to be rotating.
Step 2: Over each rotation period, if gain and phase correction is enabled, the gain and phase deviation of sine and cosine signals with respect to each other is calculated. Effect of noise and acceleration can be minimized by averaging over multiple rotations (external Resolver shaft needs to be rotating).

Only automatic gain correction can be enabled. Or automatic gain and phase correction can be enabled together. This auto gain and phase correction can also be bypassed, and manually adjusted.

Automatic Gain and Phase correction consists of two blocks: Estimation logic and Correction logic. Estimation logic can be enabled while the correction logic is either enabled or disabled. For Correction logic to be enabled the Estimation logic has to be enabled. These are controlled using the below registers.

BYPASSPHASEGAINCORRx: 0 enables estimation logic, 1 disables estimation logic. Part of register REGS_PG_EST_CFG2_x[3].
AUTOPHASECONTROLx: 0 disables correction logic, 1 enables correction logic. Part of register REGS_PG_EST_CFG2_x[2].
AUTOGAINCONTROLx: 0 disables correction logic, 1 enables correction logic. Part of register REGS_PG_EST_CFG2_x[1].
GAINCOSBYPx: 16 bit unsigned gain control for cos channel if autogaincontrol is disabled. (2¹⁴ corresponds to gain of 1). Part of register REGS_PG_EST_CFG3_x[31:16].
GAINSINBYPx: 16 bit unsigned gain control for sin channel if autogaincontrol is disabled.(2¹⁴ corresponds to gain of 1). Part of register REGS_PG_EST_CFG3_x[15:0].
PHASECOSBYPx: 16 bit signed phase control for cos channel if autophase is bypassed. (2¹⁵ corresponds to phase adjust of 90° and -2¹⁵ corresponds to phase adjust of -90°). Part of register REGS_PG_EST_CFG2_x[31:16].

AM263Px Gain and Phase Correction and Timing

Figure 7-158 Gain and Phase Correction and Timing. Gain and Phase Correction and Timing

The phase estimation and gain estimation registers can be read to monitor the estimated phase and gain values of sin and cos signals. Writing to the estimation registers to correct Phase and Gain values is also possible.

To read the estimated gain and phase values and values and calculate the analog value refer to the below formulae:

Estimated differential phase error between sin and cos (deg) = PHASEESTIMATEFINAL × 90 / (2¹⁵)
- Part of register PG_EST_CFG4_x[31:16]
Estimated analog gain of cos: √ (2²⁹ / COSSQACCFINAL)
- Part of register PG_EST_CFG5_x[31:0]
Estimated analog gain of sin : √ (2²⁹ / SINSQACCFINAL)
- Part of register PG_EST_CFG6_x[31:0]

Note:

Resolver shaft needs to be rotating for Automatic Gain and Phase Correction to work.

The estimated gain correction values for sin and cos channels will map the sin and cos data path to perfectly full 16 bits scale. In order to avoid clipping (due to noise and glitches), it is recommended to scale the gain values also.