SPRUJ62 December   2022 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J7] [J3] with LED for Status [LD4][LD5]
      2. 2.1.2 Power Control [SW1] with LED for Status [LD7][LD8][LD9]
      3. 2.1.3 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW2] [SW4] [SW13] [SW16]
      2. 2.2.2 Boot Configuration Settings [SW7] [ SW11]
      3. 2.2.3 Reset Pushbuttons [SW9] [ SW10] [SW12] [SW14]
      4. 2.2.4 User Pushbuttons [SW3] [SW5] [SW6] [SW8] [SW15] with User LED Indication [LD2] [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J48] [J49] with LED for Status [LD11] [LD12]
      2. 2.3.2 Gigabit Ethernet [J39] [J40] with Integrated LEDs for Status
      3. 2.3.3 USB3.1 Gen1 Interface [J4]
      4. 2.3.4 USB2.0 Interface [J5]
      5. 2.3.5 PCIe Card Slot [J14] [J17]
      6. 2.3.6 Display Port Interfaces [J8] [J9]
      7. 2.3.7 MicroSD Card Cage [J53]
      8. 2.3.8 Stereo Audio Interface [J29]
      9. 2.3.9 JTAG/Emulation Interface [J23] [J1]
    4. 2.4 Expansion Interfaces
      1. 2.4.1  Heatsink [ACC1] with Fan Header [J24]
      2. 2.4.2  CAN-FD Connectors [J41-J46]
      3. 2.4.3  LIN Connectors [J28]
      4. 2.4.4  Serial Ethernet Expansion Interfaces [J52] [J51]
      5. 2.4.5  Camera Interfaces [J55] [J57]
      6. 2.4.6  Automation and Control Connector [J50]
      7. 2.4.7  ADC [J27]
      8. 2.4.8  SPI [J26]
      9. 2.4.9  CSI-TX [J10]
      10. 2.4.10 Accessory Power Connector [J47]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 Power Monitoring
    6. 3.6 Shared Interfaces / Signal Muxing
    7. 3.7 Power Delivery Network (PDN)
    8. 3.8 Identification EEPROM

2.4.4 Serial Ethernet Expansion Interfaces [J52] [J51]

The EVM include dual 60-pin (3x30, 0.8-mm pitch) high speed connectors [J52] [J51] for connecting with serial Ethernet PHYs and other serial Ethernet peripherals. Each expansion connector can support up to two SGMII interfaces. The bandwidth of the SGMII interfaces are 10Gbps and 2.5Gbps. The expansion connectors(s) also include power and other IO for communicating with the Ethernet peripheral(s). The voltage levels for all control IO is 3.3 V.

Table 2-16 Serial Ethernet Expansion Pin Definition [J52] [J51]
Pin # Pin Name Description Processor Resource for [J52] / [J51] Dir
1 GND Ground
2 SGMIIa_TX_P Serial Ethernet Transmit (SGMII5 / SGMII6) Output
3 SGMIIa_TX_N Serial Ethernet Transmit (SGMII5 / SGMII6) Output
4 GND Ground
5 SGMIIa_RX_P Serial Ethernet Receive (SGMII5 / SGMII6) Input
6 SGMIIa_RX_N Serial Ethernet Receive (SGMII5 / SGMII6) Input
7 GND Ground
8 <open>
9 <open>
10 GND Ground
11 Power Power for IO Level, 3.3 V Output
12 Power Power for IO Level, 3.3 V Output
13 GND Ground
14 EEPROM_A0 Expansion EEPROM Address (A0) Output
15 EEPROM_A1 Expansion EEPROM Address (A1) Output
16 EEPROM_A2 Expansion EEPROM Address (A2) Output
17 GND Ground
18 EEPROM_WP Expansion EEPROM Write Protect Output
19 REFCLK Reference Clock, 25 MHz Output
20 GND Ground
21 EEPROM_I2C_SCL EEPROM I2C Clock (WKUP_I2C0) Output
22 EEPROM_I2C_SDA EEPROM I2C Data (WKUP_I2C0) Bi-Dir
23 GND Ground
24 I2C_SCL I2C Bus Clock (I2C0) Output
25 I2C_SDA I2C Bus Data (I2C0) Bi-Dir
26 GND Ground
27 Power Power, 12 V Output
28 Power Power, 12 V Output
29 GND Ground
30 GPIO PowerDown (IO Expander 0x22 bit P20 / bit P11) Output
31 GPIO Interrupt (WKUP_GPIO0_84 / WKUP_GPIO0_85) Input
32 GND Ground
33 SGMIIb_TX_P Serial Ethernet Transmit (SGMII1 / SGMII2) Output
34 SGMIIb_TX_N Serial Ethernet Transmit (SGMII1 / SGMII2) Output
35 GND Ground
36 SGMIIb_RX_P Serial Ethernet Receive (SGMII1 / SGMII2) Input
37 SGMIIb_RX_N Serial Ethernet Receive (SGMII1 / SGMII2) Input
38 GND Ground
39 REFCLK_N Diff Reference Clock, 125 MHz Output
40 REFCLK_P Diff Reference Clock, 125 MHz Output
41 GND Ground
42 MDIO_C MDIO Bus Clock (MDIO1) Output
43 MDIO MDIO Bus Data (MDIO1) Bi-Dir
44 GND Ground
45 GPIO Resetz (IO Expander 0x22 bit P21 / bit P24) Output
46 GPIO GPIO (IO Expander 0x22 bit P22 / bit P01) Bi-Dir
47 GPIO GPIO (IO Expander 0x22 bit P23/ bit P12) Bi-Dir
48 GND Ground
49 Power Power, 5 V Output
50 Power Power, 5 V Output
51 GND Ground
52 <open>
53 <open>
54 GND Ground
55 Power Power, 3.3 V Output
56 Power Power, 3.3 V Output
57 GND Ground
58 <open>
59 <open>
60 GND Ground
Note: In the DIR column, output is to the expansion module, input is from the expansion module. Bi-Dir signals can be configured as either input or output.