SPRUJC0 April   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Hardware Description
      1. 2.1.1 Functional Description and Connections
        1. 2.1.1.1  Power Domains
        2. 2.1.1.2  LEDs
        3. 2.1.1.3  Encoder Connectors
        4. 2.1.1.4  FSI
        5. 2.1.1.5  PGA
        6. 2.1.1.6  CAN
        7. 2.1.1.7  CLB
        8. 2.1.1.8  Boot Modes
        9. 2.1.1.9  BoosterPack Sites
        10. 2.1.1.10 Analog Voltage Reference Header
        11. 2.1.1.11 Other Headers and Jumpers
          1. 2.1.1.11.1 USB Isolation Block
          2. 2.1.1.11.2 BoosterPack Site 2 Power Isolation
          3. 2.1.1.11.3 Alternate Power
      2. 2.1.2 Debug Interface
        1. 2.1.2.1 XDS110 Debug Probe
        2. 2.1.2.2 XDS110 Output
        3. 2.1.2.3 Virtual COM Port
      3. 2.1.3 Alternate Routing
        1. 2.1.3.1 Overview
        2. 2.1.3.2 UART Routing
        3. 2.1.3.3 EQEP Routing
        4. 2.1.3.4 CAN Routing
        5. 2.1.3.5 PGA Routing
        6. 2.1.3.6 FSI Routing
        7. 2.1.3.7 X1/X2 Routing
        8. 2.1.3.8 PWM DAC
    2. 2.2 Using the F28P55x LaunchPad
    3. 2.3 BoosterPacks
    4. 2.4 Hardware Revisions
      1. 2.4.1 Revision A
  9. 3Software
    1. 3.1 Software Development
      1. 3.1.1 Software Tools and Packages
      2. 3.1.2 F28P55x LaunchPad Demo Program
      3. 3.1.3 Programming and Running Other Software on the F28P55x LaunchPad
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
      1. 4.2.1 LAUNCHXL-F28P55X Board Dimensions
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Frequently Asked Questions
    2. 5.2 Trademarks
  12. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design

2.1.1.4 FSI

The F28P55x MCU features the Fast Serial Interface (FSI) communications peripheral. The FSI enables robust high-speed communications and is intended to increase the amount of information transmitted while reducing the cost to communicate over an isolation barrier. The FSI signals TXCLK, TXD0, TXD1, RXCLK, RXD0, and RXD1 are available on J11. This header is set up in such a way that adding jumpers on the pins connects the TX to RX channels for external loopback and evaluation. Additionally, there are two GND signals on the connector that can be used for a wrapped-pair connection to an external board with FSI. The GPIOs connected to this header are only routed to the J11 FSI connector on this board, and not routed to the Boosterpack headers.

The LAUNCHXL-F28P55X does not include any on-board isolation devices for the FSI signals. If interested in evaluating the FSI peripheral with isolation devices, or differential drivers and receivers, then see the TMDSFSIADAPEVM plug on board.