SPRZ412M December   2013  – March 2023 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1

 

  1.   Abstract
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained
      4. 3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
      5. 3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1)
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
      29.      Advisory
      30.      Advisory
      31.      Advisory
      32.      Advisory
      33.      Advisory
      34.      Advisory
      35.      Advisory
      36.      Advisory
  5. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
  6. 5Silicon Revision A Usage Notes and Advisories
    1. 5.1 Silicon Revision A Usage Notes
    2. 5.2 Silicon Revision A Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
  7. 6Silicon Revision 0 Usage Notes and Advisories
    1. 6.1 Silicon Revision 0 Usage Notes
    2. 6.2 Silicon Revision 0 Advisories
      1.      Advisory
  8. 7Documentation Support
  9. 8Trademarks
  10. 9Revision History

1.2 Advisories Matrix

Table 1-2 Advisories Matrix
MODULE DESCRIPTION SILICON REVISIONS AFFECTED
0 A B C
Analog Bandgap References Yes Yes Yes Yes
Analog Trim of Some TMX Devices Yes Yes Yes
ADC ADC: ADC Post-Processing Block Limit Compare Yes Yes Yes Yes
ADC ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set Yes Yes Yes Yes
ADC ADC: ADC Offset Trim in Different Modes Yes Yes Yes Yes
ADC ADC: DMA Read of Stale Result Yes Yes Yes Yes
ADC ADC: Random Conversion Errors Yes Yes Yes
ADC ADC: ADC PPB Event Trigger (ADCxEVT) to ePWM Digital Compare Submodule Yes Yes Yes
ADC ADC: 12-Bit Switch Resistance Yes Yes Yes
ADC ADC: 12-Bit Input Capacitance When Switching Channel Groups Yes Yes Yes
ADC ADC: Functionality of VREFLO Pins Yes Yes
ADC ADC: Sensitivity to ESD Events Yes Yes
ADC ADC: ADC Input Multiplexer Connection at Beginning of Acquisition Window Yes Yes
ADC ADC: ADC Sparkle Codes Yes Yes
ADC ADC: ADC Linearity Performance Yes
XRS may Toggle During Power Up Yes Yes Yes
CLB CLB: Back-to-Back PUSH or PULL Instructions With More Than One Active High-Level Controller (HLC) Channel is Not Supported Yes Yes Yes Yes
USB USB: USB DMA Event Triggers are not Supported Yes Yes Yes Yes
VREG VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ Yes Yes Yes
Flash Flash: A Single-Bit ECC Error May Cause Endless Calls to Single-Bit-Error ISR Yes Yes Yes Yes
Flash Flash: Minimum Programming Word Size Yes Yes Yes Yes
Flash Flash: Reset of CPU2 While it has Pump Ownership Can Cause Erroneous Flash Reads From CPU1 Yes Yes
ePIE ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled Yes Yes Yes
eQEP eQEP: Position Counter Incorrectly Reset on Direction Change During Index Yes Yes Yes Yes
eQEP eQEP: eQEP Inputs in GPIO Asynchronous Mode Yes Yes Yes Yes
PLL PLL: May Not Lock on the First Lock Attempt Yes Yes Yes Yes
PLL PLL: Power Down and Bypass May Take up to 120 SYSCLK Cycles to be Effective Yes Yes Yes Yes
SDFM SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256 Yes Yes Yes Yes
SDFM SDFM: Spurious Data Acknowledge Event When Data Filter is Configured and Enabled for the First Time Yes Yes Yes Yes
SDFM SDFM: Spurious Data Acknowledge Event When Data Filter is Synchronized Using PWM FILRES Signal Yes Yes Yes Yes
SDFM SDFM: Comparator Filter Module may Generate Spurious Over-Value and Under-Value Conditions Yes Yes Yes Yes
SDFM SDFM: Dynamically Changing Threshold Settings (LLT, HLT), Filter Type, or COSR Settings Will Trigger Spurious Comparator Events Yes Yes Yes Yes
SDFM SDFM: Dynamically Changing Data Filter Settings (Such as Filter Type or DOSR) Will Trigger Spurious Data Acknowledge Events Yes Yes Yes Yes
SDFM SDFM: Manchester Mode (Mode 2) Does Not Produce Correct Filter Results Under Several Conditions Yes Yes Yes Yes
FPU FPU: FPU-to-CPU Register Move Operation Preceded by Any FPU 2p Operation Yes Yes Yes Yes
FPU FPU: LUF, LVF Flags are Invalid for the EINVF32 and EISQRTF32 Instructions Yes Yes Yes Yes
Memory Memory: Prefetching Beyond Valid Memory Yes Yes Yes Yes
INTOSC INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift Yes Yes Yes Yes
Low-Power Modes Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity Yes Yes Yes Yes
I2C I2C: SDA and SCL Open-Drain Output Buffer Issue Yes Yes Yes Yes
ePWM ePWM: An ePWM Glitch can Occur if a Trip Remains Active at the End of the Blanking Window Yes Yes Yes Yes
ePWM ePWM: ePWM Dead-Band Delay Value Cannot be Set to 0 When Using Shadow Load Mode for RED/FED Yes Yes Yes Yes
ePWM ePWM: Trip Events Will Not be Filtered by the Blanking Window for the First 3 Cycles After the Start of a Blanking Window Yes Yes Yes Yes
SYSTEM SYSTEM: Multiple Successive Writes to CLKSRCCTL1 Can Cause a System Hang Yes Yes Yes Yes
CMPSS CMPSS: COMPxLATCH May Not Clear Properly Under Certain Conditions Yes Yes Yes Yes
CMPSS CMPSS: Ramp Generator May Not Start Under Certain Conditions Yes Yes Yes Yes
CMPSS CMPSS: CMPIN4N, CMPIN4P, CMPIN5N, and CMPIN5P Not Available Yes Yes
GPIO GPIO: Open-Drain Configuration May Drive a Short High Pulse Yes Yes Yes Yes
GPIO GPIO: GPIO0–GPIO7, GPIO46, GPIO47 Shunt to VSS Due to Fast Transients at High Temperature Yes Yes
During DCAN FIFO Mode, Received Messages May be Placed Out of Order in the FIFO Buffer Yes Yes Yes Yes
Boot ROM Boot ROM: Calling SCI Bootloader from Application Yes Yes Yes Yes
Boot ROM Boot ROM: Using CPU1 Wait Boot or CPU2 Idle Mode Yes Yes Yes Yes
Boot ROM Boot ROM: Device Will Hang During Boot if X1 Clock Source is not Present Yes
HRPWM HRPWM: HRCNFG Register Reads and Bit-Wise Writes Yes Yes
SYSBIOS SYSBIOS in ROM References Different Flash Sector (Changed From Sector A to Sector B) Yes Yes
McBSP McBSP: McBSP Transmit in SPI Slave Mode Yes Yes
Crystal Crystal: Maximum Equivalent Series Resistance (ESR) Values are Reduced Yes Yes