SWCU191 February 2022 CC1311P3 , CC1311R3 , CC2651P3 , CC2651R3 , CC2651R3SIPA
During an SRAM write, a parity bit is calculated and stored for each byte that is written. Parity error detection is done on a byte-wide basis during an SRAM read operation. This means that a parity error on any byte in a memory read operation causes a memory data error to be detected. A parity error causes a processor bus fault exception (see Section 6.1.2).
The SRAM address that was read during parity error detection is captured in the SRAM_MMR:PER_CHK register. This parity error address is stored as an offset from the base address of SRAM memory.