SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
3.2 Block Diagram
Figure 3-1 shows the core processor unit (CPU) block diagram. The Arm® Cortex®-M4F processor is built on a high-performance processor core with a 3-stage pipeline Harvard architecture, thus it is ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, which provides high-end processing hardware. The instruction set includes a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic, and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Arm® Cortex®-M4F processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system-debug capabilities. The Arm® Cortex®-M4F processor implements a version of the Thumb instruction set based on Thumb-2 technology; thus ensuring high code density and reduced program-memory requirements. The Arm® Cortex®-M4F instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Arm® Cortex®-M4F processor closely integrates a nested vector interrupt controller (NVIC) to deliver fast execution of interrupt service routines (ISRs) thereby dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduces interrupt latency. Interrupt handlers do not require any assembler stubs, thus removing code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including deep-sleep mode, which enables the entire device to be rapidly powered down.
Figure 3-1 CPU Block Diagram