SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
16.3.2.3 Input Edge-Time Mode
For rising-edge detection, the input signal must be high for at least two system-clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be low for at least two system-clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is ¼ of the system frequency.
In edge-time mode, the timer is configured as a 24-bit down counter, including the optional prescaler with the upper timer value stored in the GPT:TnPR register and the lower bits in the GPT:TnILR register. In this mode, the timer is initialized to the value loaded in the GPT:TnILR and the GPT:TnPR registers when counting down and 0x0 when counting up. The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into edge-time mode by setting the GPT:TnMR TnCM register bit, and the type of event that the timer captures is determined by the GPT:CTL TnEVENT register fields. Table 16-4 lists the values that are loaded into the timer registers when the timer is enabled.
| Register | Count Down Mode | Count Up Mode |
|---|---|---|
| GPT:TnR | GPT:TnILR | 0x0 |
| GPT:TnV | GPT:TnILR | 0x0 |
| GPT:TnPV | GPT:TnPR | 0x0 |
When software writes to the GPT:CTL TnEN register bit, the timer is enabled for event capture. When the selected input event is detected, the current timer counter value is captured in the GPT:TnR register and is available to be read by the microcontroller. The GPTM then asserts the GPTM Raw Interrupt Status register (GPT:RIS) CnERIS bit, and holds the bit until it is cleared by writing the GPTM Interrupt Clear register (GPT:ICR). If the capture mode event interrupt is enabled in the GPTM Interrupt Mask register (GPT:IMR), the GPTM also sets the GPTM Masked Interrupt Status register (GPT:MIS) CnEMIS bit. In this mode, the GPT:TnR register holds the time at which the selected input event occurred, while the GPT:TnV and the GPT:TnPV registers hold the free-running timer value and the free-running prescaler value. These registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR.
In addition to generating interrupts a μDMA trigger can be generated. This trigger is enabled by configuring and enabling the appropriate μDMA channel.
After an event has been captured, the timer does not stop counting. The timer continues to count until the TnEN bit is cleared. When the timer reaches the timeout value, it is reloaded with 0x0 in up-count mode, and the value from the GPT:TnILR and the GPT:TnPR registers in down-count mode.
Figure 16-3 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising-edge events.
Each time a rising-edge event is detected, the current count value is loaded into the GPTIMER:TnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into the GPT:TnR register).
Figure 16-3 Input Edge-Time Mode ExampleWhen operating in edge-time mode, the counter uses a modulo 224 count if prescaler is enabled, or 216 if prescaler is not enabled. If there is a possibility the edge could take longer than the count, another timer can be used to ensure detection of the missed edge.