SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

4.6 EVTSVT Registers

Table 4-13 lists the memory-mapped registers for the EVTSVT registers. All register offset addresses not listed in Table 4-13 should be considered as reserved locations and the register contents should not be modified.

Table 4-13 EVTSVT Registers
OffsetAcronymRegister NameSection
0hDESCDescriptionGo
4hDESCEXExtended DescriptionGo
64hDTBDigital test bus controlGo
400hNMISELOutput Selection for CPU NMI ExceptionGo
404hCPUIRQ0SELOutput Selection for CPU Interrupt CPUIRQ0Go
408hCPUIRQ1SELOutput Selection for CPU Interrupt CPUIRQ1Go
40ChCPUIRQ2SELOutput Selection for CPU Interrupt CPUIRQ2Go
410hCPUIRQ3SELOutput Selection for CPU Interrupt CPUIRQ3Go
414hCPUIRQ4SELOutput Selection for CPU Interrupt CPUIRQ4Go
418hCPUIRQ5SELOutput Selection for CPU Interrupt CPUIRQ5Go
41ChCPUIRQ6SELOutput Selection for CPU Interrupt CPUIRQ6Go
420hCPUIRQ7SELOutput Selection for CPU Interrupt CPUIRQ7Go
424hCPUIRQ8SELOutput Selection for CPU Interrupt CPUIRQ8Go
428hCPUIRQ9SELOutput Selection for CPU Interrupt CPUIRQ9Go
42ChCPUIRQ10SELOutput Selection for CPU Interrupt CPUIRQ10Go
430hCPUIRQ11SELOutput Selection for CPU Interrupt CPUIRQ11Go
434hCPUIRQ12SELOutput Selection for CPU Interrupt CPUIRQ12Go
438hCPUIRQ13SELOutput Selection for CPU Interrupt CPUIRQ13Go
43ChCPUIRQ14SELOutput Selection for CPU Interrupt CPUIRQ14Go
440hCPUIRQ15SELOutput Selection for CPU Interrupt CPUIRQ15Go
444hCPUIRQ16SELOutput Selection for CPU Interrupt CPUIRQ16Go
448hCPUIRQ17SELOutput Selection for CPU Interrupt CPUIRQ17Go
44ChCPUIRQ18SELOutput Selection for CPU Interrupt CPUIRQ18Go
450hSYSTIMC0SELOutput Selection for SYSTIMC0Go
454hSYSTIMC1SELOutput Selection for SYSTIMC1Go
458hSYSTIMC2SELOutput Selection for SYSTIMC2Go
45ChSYSTIMC3SELOutput Selection for SYSTIMC3Go
460hSYSTIMC4SELOutput Selection for SYSTIMC4Go
464hADCTRGSELOutput Selection for ADCTRGGo
468hLGPTSYNCSELOutput Selection for LGPTSYNCGo
46ChLGPT0IN0SELOutput Selection for LGPT0IN0Go
470hLGPT0IN1SELOutput Selection for LGPT0IN1Go
474hLGPT0IN2SELOutput Selection for LGPT0IN2Go
478hLGPT0TENSELOutput Selection for LGPT0TENGo
47ChLGPT1IN0SELOutput Selection for LGPT1IN0Go
480hLGPT1IN1SELOutput Selection for LGPT1IN1Go
484hLGPT1IN2SELOutput Selection for LGPT1IN2Go
488hLGPT1TENSELOutput Selection for LGPT1TENGo
48ChLGPT2IN0SELOutput Selection for LGPT2IN0Go
490hLGPT2IN1SELOutput Selection for LGPT2IN1Go
494hLGPT2IN2SELOutput Selection for LGPT2IN2Go
498hLGPT2TENSELOutput Selection for LGPT2TENGo
49ChLGPT3IN0SELOutput Selection for LGPT3IN0Go
4A0hLGPT3IN1SELOutput Selection for LGPT3IN1Go
4A4hLGPT3IN2SELOutput Selection for LGPT3IN2Go
4A8hLGPT3TENSELOutput Selection for LGPT3TENGo
4AChLRFDIN0SELOutput Selection for LRFDIN0Go
4B0hLRFDIN1SELOutput Selection for LRFDIN1Go
4B4hLRFDIN2SELOutput Selection for LRFDIN2Go
C00hDMACH0SELOutput Selection for DMA CH0Go
C04hDMACH1SELOutput Selection for DMA CH1Go
C08hDMACH2SELOutput Selection for DMA CH2Go
C0ChDMACH3SELOutput Selection for DMA CH3Go
C10hDMACH4SELOutput Selection for DMA CH4Go
C14hDMACH5SELOutput Selection for DMA CH5Go
C18hDMACH6SELOutput Selection for DMA CH6Go
C1ChDMACH7SELOutput Selection for DMA CH7Go

Complex bit access types are encoded to fit into small table cells. Table 4-14 shows the codes that are used for access types in this section.

Table 4-14 EVTSVT Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

4.6.1 DESC Register (Offset = 0h) [Reset = 30451010h]

DESC is shown in Table 4-15.

Return to the Summary Table.

Description

This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 4-15 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR3045hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

4.6.2 DESCEX Register (Offset = 4h) [Reset = 02182D31h]

DESCEX is shown in Table 4-16.

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Extended Description

This register provides configuration details of the IP to software drivers and end users.

Table 4-16 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-22IDMAR8hNumber of DMA input channels
21-17NDMARChNumber of DMA output channels
16PDR0hPower Domain.
0 : SVT
1 : ULL
15-8NSUBR2DhNumber of Subscribers
7-0NPUBR31hNumber of Publishers

4.6.3 DTB Register (Offset = 64h) [Reset = 00000000h]

DTB is shown in Table 4-17.

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Digital test bus control

This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.

Table 4-17 DTB Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
1-0SELR/W0hDigital test bus selection mux control.
Non-zero select values output a 16 bit selected group of signals per value.

4.6.4 NMISEL Register (Offset = 400h) [Reset = 00000000h]

NMISEL is shown in Table 4-18.

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Output Selection for CPU NMI Exception

Table 4-18 NMISEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
1h = Selects an AON_NMI source, controlled by EVTULL:NMISEL
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.5 CPUIRQ0SEL Register (Offset = 404h) [Reset = 00000000h]

CPUIRQ0SEL is shown in Table 4-19.

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Output Selection for CPU Interrupt CPUIRQ0

Table 4-19 CPUIRQ0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.6 CPUIRQ1SEL Register (Offset = 408h) [Reset = 00000000h]

CPUIRQ1SEL is shown in Table 4-20.

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Output Selection for CPU Interrupt CPUIRQ1

Table 4-20 CPUIRQ1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.7 CPUIRQ2SEL Register (Offset = 40Ch) [Reset = 00000000h]

CPUIRQ2SEL is shown in Table 4-21.

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Output Selection for CPU Interrupt CPUIRQ2

Table 4-21 CPUIRQ2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS

4.6.8 CPUIRQ3SEL Register (Offset = 410h) [Reset = 00000000h]

CPUIRQ3SEL is shown in Table 4-22.

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Output Selection for CPU Interrupt CPUIRQ3

Table 4-22 CPUIRQ3SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS

4.6.9 CPUIRQ4SEL Register (Offset = 414h) [Reset = 00000000h]

CPUIRQ4SEL is shown in Table 4-23.

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Output Selection for CPU Interrupt CPUIRQ4

Table 4-23 CPUIRQ4SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS

4.6.10 CPUIRQ5SEL Register (Offset = 418h) [Reset = 00000009h]

CPUIRQ5SEL is shown in Table 4-24.

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Output Selection for CPU Interrupt CPUIRQ5

Table 4-24 CPUIRQ5SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR9hRead only selection value
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS

4.6.11 CPUIRQ6SEL Register (Offset = 41Ch) [Reset = 0000000Ch]

CPUIRQ6SEL is shown in Table 4-25.

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Output Selection for CPU Interrupt CPUIRQ6

Table 4-25 CPUIRQ6SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDRChRead only selection value
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0

4.6.12 CPUIRQ7SEL Register (Offset = 420h) [Reset = 0000000Dh]

CPUIRQ7SEL is shown in Table 4-26.

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Output Selection for CPU Interrupt CPUIRQ7

Table 4-26 CPUIRQ7SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDRDhRead only selection value
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1

4.6.13 CPUIRQ8SEL Register (Offset = 424h) [Reset = 00000014h]

CPUIRQ8SEL is shown in Table 4-27.

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Output Selection for CPU Interrupt CPUIRQ8

Table 4-27 CPUIRQ8SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR14hRead only selection value
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE

4.6.14 CPUIRQ9SEL Register (Offset = 428h) [Reset = 00000016h]

CPUIRQ9SEL is shown in Table 4-28.

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Output Selection for CPU Interrupt CPUIRQ9

Table 4-28 CPUIRQ9SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR16hRead only selection value
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS

4.6.15 CPUIRQ10SEL Register (Offset = 42Ch) [Reset = 0000000Fh]

CPUIRQ10SEL is shown in Table 4-29.

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Output Selection for CPU Interrupt CPUIRQ10

Table 4-29 CPUIRQ10SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDRFhRead only selection value
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS

4.6.16 CPUIRQ11SEL Register (Offset = 430h) [Reset = 00000017h]

CPUIRQ11SEL is shown in Table 4-30.

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Output Selection for CPU Interrupt CPUIRQ11

Table 4-30 CPUIRQ11SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR17hRead only selection value
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS

4.6.17 CPUIRQ12SEL Register (Offset = 434h) [Reset = 00000018h]

CPUIRQ12SEL is shown in Table 4-31.

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Output Selection for CPU Interrupt CPUIRQ12

Table 4-31 CPUIRQ12SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR18hRead only selection value
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS

4.6.18 CPUIRQ13SEL Register (Offset = 438h) [Reset = 00000012h]

CPUIRQ13SEL is shown in Table 4-32.

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Output Selection for CPU Interrupt CPUIRQ13

Table 4-32 CPUIRQ13SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR12hRead only selection value
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS

4.6.19 CPUIRQ14SEL Register (Offset = 43Ch) [Reset = 00000013h]

CPUIRQ14SEL is shown in Table 4-33.

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Output Selection for CPU Interrupt CPUIRQ14

Table 4-33 CPUIRQ14SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR13hRead only selection value
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS

4.6.20 CPUIRQ15SEL Register (Offset = 440h) [Reset = 00000010h]

CPUIRQ15SEL is shown in Table 4-34.

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Output Selection for CPU Interrupt CPUIRQ15

Table 4-34 CPUIRQ15SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR10hRead only selection value
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0

4.6.21 CPUIRQ16SEL Register (Offset = 444h) [Reset = 00000000h]

CPUIRQ16SEL is shown in Table 4-35.

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Output Selection for CPU Interrupt CPUIRQ16

Table 4-35 CPUIRQ16SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.22 CPUIRQ17SEL Register (Offset = 448h) [Reset = 00000031h]

CPUIRQ17SEL is shown in Table 4-36.

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Output Selection for CPU Interrupt CPUIRQ17

Table 4-36 CPUIRQ17SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR31hRead only selection value
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS

4.6.23 CPUIRQ18SEL Register (Offset = 44Ch) [Reset = 00000037h]

CPUIRQ18SEL is shown in Table 4-37.

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Output Selection for CPU Interrupt CPUIRQ18

Table 4-37 CPUIRQ18SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR37hRead only selection value
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS

4.6.24 SYSTIMC0SEL Register (Offset = 450h) [Reset = 00000004h]

SYSTIMC0SEL is shown in Table 4-38.

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Output Selection for SYSTIMC0

Table 4-38 SYSTIMC0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR4hRead only selection value
4h = AON_RTC event, controlled by the RTC:IMASK setting

4.6.25 SYSTIMC1SEL Register (Offset = 454h) [Reset = 00000000h]

SYSTIMC1SEL is shown in Table 4-39.

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Output Selection for SYSTIMC1

Table 4-39 SYSTIMC1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.26 SYSTIMC2SEL Register (Offset = 458h) [Reset = 0000002Ah]

SYSTIMC2SEL is shown in Table 4-40.

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Output Selection for SYSTIMC2

Table 4-40 SYSTIMC2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR2AhRead only selection value
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0

4.6.27 SYSTIMC3SEL Register (Offset = 45Ch) [Reset = 0000002Bh]

SYSTIMC3SEL is shown in Table 4-41.

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Output Selection for SYSTIMC3

Table 4-41 SYSTIMC3SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR2BhRead only selection value
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1

4.6.28 SYSTIMC4SEL Register (Offset = 460h) [Reset = 0000002Ch]

SYSTIMC4SEL is shown in Table 4-42.

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Output Selection for SYSTIMC4

Table 4-42 SYSTIMC4SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR2ChRead only selection value
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2

4.6.29 ADCTRGSEL Register (Offset = 464h) [Reset = 00000000h]

ADCTRGSEL is shown in Table 4-43.

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Output Selection for ADCTRG

Table 4-43 ADCTRGSEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.30 LGPTSYNCSEL Register (Offset = 468h) [Reset = 00000000h]

LGPTSYNCSEL is shown in Table 4-44.

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Output Selection for LGPTSYNC

Table 4-44 LGPTSYNCSEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.31 LGPT0IN0SEL Register (Offset = 46Ch) [Reset = 00000000h]

LGPT0IN0SEL is shown in Table 4-45.

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Output Selection for LGPT0IN0

Table 4-45 LGPT0IN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.32 LGPT0IN1SEL Register (Offset = 470h) [Reset = 00000000h]

LGPT0IN1SEL is shown in Table 4-46.

Return to the Summary Table.

Output Selection for LGPT0IN1

Table 4-46 LGPT0IN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.33 LGPT0IN2SEL Register (Offset = 474h) [Reset = 00000000h]

LGPT0IN2SEL is shown in Table 4-47.

Return to the Summary Table.

Output Selection for LGPT0IN2

Table 4-47 LGPT0IN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.34 LGPT0TENSEL Register (Offset = 478h) [Reset = 00000000h]

LGPT0TENSEL is shown in Table 4-48.

Return to the Summary Table.

Output Selection for LGPT0TEN

Table 4-48 LGPT0TENSEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.35 LGPT1IN0SEL Register (Offset = 47Ch) [Reset = 00000000h]

LGPT1IN0SEL is shown in Table 4-49.

Return to the Summary Table.

Output Selection for LGPT1IN0

Table 4-49 LGPT1IN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.36 LGPT1IN1SEL Register (Offset = 480h) [Reset = 00000000h]

LGPT1IN1SEL is shown in Table 4-50.

Return to the Summary Table.

Output Selection for LGPT1IN1

Table 4-50 LGPT1IN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.37 LGPT1IN2SEL Register (Offset = 484h) [Reset = 00000000h]

LGPT1IN2SEL is shown in Table 4-51.

Return to the Summary Table.

Output Selection for LGPT1IN2

Table 4-51 LGPT1IN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.38 LGPT1TENSEL Register (Offset = 488h) [Reset = 00000000h]

LGPT1TENSEL is shown in Table 4-52.

Return to the Summary Table.

Output Selection for LGPT1TEN

Table 4-52 LGPT1TENSEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.39 LGPT2IN0SEL Register (Offset = 48Ch) [Reset = 00000000h]

LGPT2IN0SEL is shown in Table 4-53.

Return to the Summary Table.

Output Selection for LGPT2IN0

Table 4-53 LGPT2IN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.40 LGPT2IN1SEL Register (Offset = 490h) [Reset = 00000000h]

LGPT2IN1SEL is shown in Table 4-54.

Return to the Summary Table.

Output Selection for LGPT2IN1

Table 4-54 LGPT2IN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.41 LGPT2IN2SEL Register (Offset = 494h) [Reset = 00000000h]

LGPT2IN2SEL is shown in Table 4-55.

Return to the Summary Table.

Output Selection for LGPT2IN2

Table 4-55 LGPT2IN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.42 LGPT2TENSEL Register (Offset = 498h) [Reset = 00000000h]

LGPT2TENSEL is shown in Table 4-56.

Return to the Summary Table.

Output Selection for LGPT2TEN

Table 4-56 LGPT2TENSEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.43 LGPT3IN0SEL Register (Offset = 49Ch) [Reset = 00000000h]

LGPT3IN0SEL is shown in Table 4-57.

Return to the Summary Table.

Output Selection for LGPT3IN0

Table 4-57 LGPT3IN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.44 LGPT3IN1SEL Register (Offset = 4A0h) [Reset = 00000000h]

LGPT3IN1SEL is shown in Table 4-58.

Return to the Summary Table.

Output Selection for LGPT3IN1

Table 4-58 LGPT3IN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.45 LGPT3IN2SEL Register (Offset = 4A4h) [Reset = 00000000h]

LGPT3IN2SEL is shown in Table 4-59.

Return to the Summary Table.

Output Selection for LGPT3IN2

Table 4-59 LGPT3IN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.46 LGPT3TENSEL Register (Offset = 4A8h) [Reset = 00000000h]

LGPT3TENSEL is shown in Table 4-60.

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Output Selection for LGPT3TEN

Table 4-60 LGPT3TENSEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.47 LRFDIN0SEL Register (Offset = 4ACh) [Reset = 0000001Dh]

LRFDIN0SEL is shown in Table 4-61.

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Output Selection for LRFDIN0

Table 4-61 LRFDIN0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR1DhRead only selection value
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2

4.6.48 LRFDIN1SEL Register (Offset = 4B0h) [Reset = 0000001Eh]

LRFDIN1SEL is shown in Table 4-62.

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Output Selection for LRFDIN1

Table 4-62 LRFDIN1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR1EhRead only selection value
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3

4.6.49 LRFDIN2SEL Register (Offset = 4B4h) [Reset = 0000001Fh]

LRFDIN2SEL is shown in Table 4-63.

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Output Selection for LRFDIN2

Table 4-63 LRFDIN2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR1FhRead only selection value
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4

4.6.50 DMACH0SEL Register (Offset = C00h) [Reset = 00000000h]

DMACH0SEL is shown in Table 4-64.

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Output Selection for DMA CH0

Table 4-64 DMACH0SEL Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
2-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Selects spi0txtrg as channel source
7h = Selects uart0rxtrg as channel source

4.6.51 DMACH1SEL Register (Offset = C04h) [Reset = 00000000h]

DMACH1SEL is shown in Table 4-65.

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Output Selection for DMA CH1

Table 4-65 DMACH1SEL Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
2-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
1h = Selects spi0rxtrg as channel source
6h = Selects uart0txtrg as channel source

4.6.52 DMACH2SEL Register (Offset = C08h) [Reset = 00000000h]

DMACH2SEL is shown in Table 4-66.

Return to the Summary Table.

Output Selection for DMA CH2

Table 4-66 DMACH2SEL Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
2-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
2h = Reserved value. Should not be programmed.
6h = Selects uart0txtrg as channel source

4.6.53 DMACH3SEL Register (Offset = C0Ch) [Reset = 00000000h]

DMACH3SEL is shown in Table 4-67.

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Output Selection for DMA CH3

Table 4-67 DMACH3SEL Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
2-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
5h = Selects adc0trg as channel source
7h = Selects uart0rxtrg as channel source

4.6.54 DMACH4SEL Register (Offset = C10h) [Reset = 00000000h]

DMACH4SEL is shown in Table 4-68.

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Output Selection for DMA CH4

Table 4-68 DMACH4SEL Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
2-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
2h = Reserved value. Should not be programmed.
3h = Selects laestrga as channel source

4.6.55 DMACH5SEL Register (Offset = C14h) [Reset = 00000000h]

DMACH5SEL is shown in Table 4-69.

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Output Selection for DMA CH5

Table 4-69 DMACH5SEL Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-3RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
2-0IPIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
4h = Selects laestrgb as channel source
5h = Selects adc0trg as channel source

4.6.56 DMACH6SEL Register (Offset = C18h) [Reset = 00000000h]

DMACH6SEL is shown in Table 4-70.

Return to the Summary Table.

Output Selection for DMA CH6

Table 4-70 DMACH6SEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
16EDGDETDISR/W0hEdge detect disable.
0: Enabled.
1: Disabled
15-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting

4.6.57 DMACH7SEL Register (Offset = C1Ch) [Reset = 00000000h]

DMACH7SEL is shown in Table 4-71.

Return to the Summary Table.

Output Selection for DMA CH7

Table 4-71 DMACH7SEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
16EDGDETDISR/W0hEdge detect disable.
0: Enabled.
1: Disabled
15-6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior
5-0PUBIDR/W0hRead/write selection value.
Writing any other value than values defined by a ENUM may result in undefined behavior.
0h = Always inactive
2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT
3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS
4h = AON_RTC event, controlled by the RTC:IMASK setting
5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS
6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG
7h = IOC synchronous combined event, controlled by IOC:EVTCFG
8h = SYSTIM combined interrupt, interrupt flags are found here SYSTIM:MIS
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Ah = GPIO generic published event, controlled by GPIO:EVTCFG
Bh = NoWrapper Flash interrupt indicating that the flash operation has completed, interrupt flags can be found here FLASH:MIS
Ch = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS0
Dh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS1
Eh = LRFD combined event, interrupt flags can be found here LRFDDBELL:MIS2
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
10h = ADC combined interrupt request, interrupt flags can be found here ADC:MIS0
11h = ADC general published event, interrupt flags can be found here ADC:MIS1
12h = LGPT0 combined interrupt, interrupt flags are found here LGPT0:MIS
13h = LGPT1 combined interrupt, interrupt flags are found here LGPT1:MIS
14h = DMA combined done interrupt, corresponding flags can be found here DMA:REQDONE
15h = DMA bus error, corresponds to DMA:ERROR.STATUS
16h = AES accelerator combined interrupt request, interrupt flags can be found here AES:MIS
17h = UART0 combined interrupt, interrupt flags are found here UART0:MIS
18h = Interrupt event from I2C0, interrupt flags can be found here I2C0:MIS
19h = SYSTIM heartbeat, can be set by SYSTIM:TIMEBIT
1Ah = SYSTIM interrupt driven by synchronizing LFTICK signal to SVT clock
1Bh = SYSTIM Channel 0 event, event flag is SYSTIM:MIS.EVT0
1Ch = SYSTIM Channel 1 event, event flag is SYSTIM:MIS.EVT1
1Dh = SYSTIM Channel 2 event, event flag is SYSTIM:MIS.EVT2
1Eh = SYSTIM Channel 3 event, event flag is SYSTIM:MIS.EVT3
1Fh = SYSTIM Channel 4 event, event flag is SYSTIM:MIS.EVT4
20h = LGPT0 compare/capture output event 0, controlled by LGPT0:C0CFG setting
21h = LGPT0 compare/capture output event 1, controlled by LGPT0:C1CFG setting
22h = LGPT0 compare/capture output event 2, controlled by LGPT0:C2CFG setting
23h = LGPT0 DMA request event, controlled by LGPT0:DMA setting
24h = LGPT0 ADC trigger event, controlled by LGPT0:ADCTRG setting
25h = LGPT1 compare/capture output event 0, controlled by LGPT1:C0CFG setting
26h = LGPT1 compare/capture output event 1, controlled by LGPT1:C1CFG setting
27h = LGPT1 compare/capture output event 2, controlled by LGPT1:C2CFG setting
28h = LGPT1 DMA request event, controlled by LGPT1:DMA setting
29h = LGPT1 ADC trigger event, controlled by LGPT1:ADCTRG setting
2Ah = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC0
2Bh = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC1
2Ch = LRFD interrupt to SYSTIM, controlled by LRFDDBELL:SYSTIMOEV.SRC2
2Eh = LGPT2 compare/capture output event 0, controlled by LGPT2:C0CFG setting
2Fh = LGPT2 compare/capture output event 1, controlled by LGPT2:C1CFG setting
30h = LGPT0 compare/capture output event 2, controlled by LGPT2:C2CFG setting
31h = LGPT2 combined interrupt, interrupt flags are found here LGPT2:MIS
32h = LGPT2 DMA request event, controlled by LGPT2:DMA setting
33h = LGPT2 ADC trigger event, controlled by LGPT2:ADCTRG setting
34h = LGPT3 compare/capture output event 0, controlled by LGPT3:C0CFG setting
35h = LGPT3 compare/capture output event 1, controlled by LGPT3:C1CFG setting
36h = LGPT3 compare/capture output event 2, controlled by LGPT3:C2CFG setting
37h = LGPT3 combined interrupt, interrupt flags are found here LGPT3:MIS
38h = LGPT3 DMA request event, controlled by LGPT3:DMA setting
39h = LGPT3 ADC trigger event, controlled by LGPT3:ADCTRG setting