SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

11.4 SYSTIM Registers

Table 11-1 lists the memory-mapped registers for the SYSTIM registers. All register offset addresses not listed in Table 11-1 should be considered as reserved locations and the register contents should not be modified.

Table 11-1 SYSTIM Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionGo
44hIMASKInterrupt maskGo
48hRISRaw interrupt statusGo
4ChMISMasked interrupt statusGo
50hISETInterrupt setGo
54hICLRInterrupt clearGo
58hIMSETInterrupt mask setGo
5ChIMCLRInterrupt mask clearGo
60hEMUEmulationGo
100hTIME250NSystime Count Value [31:0]Go
104hTIME1USystime Count Value [33:2]Go
108hOUTchannel's Ouput ValueGo
10ChCH0CFGchannel0 Configuration.Go
110hCH1CFGchannel1 Configuration.Go
114hCH2CFGchannel2 Configuration.Go
118hCH3CFGchannel3 Configuration.Go
11ChCH4CFGchannel4 Configuration.Go
120hCH0CCChannel 0 Capture/Compare ValueGo
124hCH1CCChannel 1 Capture/Compare ValueGo
128hCH2CCChannel 2 Capture/Compare ValueGo
12ChCH3CCChannel 3 Capture/Compare ValueGo
130hCH4CCChannel 4 Capture/Compare ValueGo
134hTIMEBITSystimer's Time bitGo
140hSTATUSTimer StatusGo
144hARMSETChannel arming setGo
148hARMCLRChannel Arming clearGo
14ChCH0CCSRChannel 0 Save/Restore ValueGo
150hCH1CCSRChannel 1 Save/Restore ValueGo
154hCH2CCSRChannel 2 Save/Restore ValueGo
158hCH3CCSRChannel 3 Save/Restore ValueGo
15ChCH4CCSRChannel 4 Save/Restore ValueGo

Complex bit access types are encoded to fit into small table cells. Table 11-2 shows the codes that are used for access types in this section.

Table 11-2 SYSTIM Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

11.4.1 DESC Register (Offset = 0h) [Reset = 94431010h]

DESC is shown in Table 11-3.

Return to the Summary Table.

Description.
This register identifies the peripheral and its exact version.

Table 11-3 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR9443hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exists in SOC, this field can identify the instance number 0-15
7-4MAJREVR1hMajor revision of IP 0-15
3-0MINREVR0hMinor revision of IP 0-15.

11.4.2 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 11-4.

Return to the Summary Table.

Interrupt mask.
This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 11-4 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5OVFLR/W0hSystimer counter overflow event interrupt mask.
0h = Disable Interrupt Mask
1h = Enable Interrrupt Mask
4EV4R/W0hSystimer channel 4 event interrupt mask.
0h = Disable Interrupt Mask
1h = Enable Interrrupt Mask
3EV3R/W0hSystimer channel 3 event interrupt mask.
0h = Disable Interrupt Mask
1h = Enable Interrrupt Mask
2EV2R/W0hSystimer channel 2 event interrupt mask.
0h = Disable Interrupt Mask
1h = Enable Interrrupt Mask
1EV1R/W0hSystimer channel 1 event interrupt mask.
0h = Disable Interrupt Mask
1h = Enable Interrrupt Mask
0EV0R/W0hSystimer channel 0 event interrupt mask.
0h = Disable Interrupt Mask
1h = Enable Interrrupt Mask

11.4.3 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 11-5.

Return to the Summary Table.

Raw interrupt status.
This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 11-5 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5OVFLR0hRaw interrupt status for Systimer counter overflow event.
This bit is set to 1 when an event is received on SysTimer Overflow occurs.
0h = Interrupt did not occur
1h = Interrupt occured
4EV4R0hRaw interrupt status for channel 4 event.
This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 4.
0h = Interrupt did not occur
1h = Interrupt occured
3EV3R0hRaw interrupt status for channel 3 event.
This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 3.
0h = Interrupt did not occur
1h = Interrupt occured
2EV2R0hRaw interrupt status for channel 2 Event.
This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 2.
0h = Interrupt did not occur
1h = Interrupt occured
1EV1R0hRaw interrupt status for channel 1 event.
This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 1.
0h = Interrupt did not occur
1h = Interrupt occured
0EV0R0hRaw interrupt status for channel 0 event.
This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 0.
0h = Interrupt did not occur
1h = Interrupt occured

11.4.4 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 11-6.

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Masked interrupt status.
This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 11-6 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5OVFLR0hMask Interrupt status for Systimer counter overflow Event in MIS register.
0h = Interrupt did not occur
1h = Interrupt occured
4EV4R0hMask interrupt status for channel 4 event.
0h = Interrupt did not occur
1h = Interrupt occured
3EV3R0hMask interrupt status for channel 3 event.
0h = Interrupt did not occur
1h = Interrupt occured
2EV2R0hMask interrupt status for channel 2 event.
0h = Interrupt did not occur
1h = Interrupt occured
1EV1R0hMask interrupt status for channel 1 event.
0h = Interrupt did not occur
1h = Interrupt occured
0EV0R0hMask interrupt status for channel 0 event.
0h = Interrupt did not occur
1h = Interrupt occured

11.4.5 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 11-7.

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Interrupt set.

This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 11-7 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5OVFLW0hSets Systimer counter overflow interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
4EV4W0hSets channel 4 interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
3EV3W0hSets channel 3 interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
2EV2W0hSets channel 2 interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
1EV1W0hSets channel 1 interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt
0EV0W0hSets channel 0 interrupt.
0h = Writing 0 has no effect
1h = Set Interrupt

11.4.6 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 11-8.

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Interrupt clear.
'This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 11-8 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5OVFLW0hClears Systimer counter overflow interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
4EV4W0hClears channel 4 interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
3EV3W0hClears channel 3 interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
2EV2W0hClears channel 2 interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
1EV1W0hClears channel 1 interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt
0EV0W0hClears channel 0 interrupt.
0h = Writing 0 has no effect
1h = Clear Interrupt

11.4.7 IMSET Register (Offset = 58h) [Reset = 00000000h]

IMSET is shown in Table 11-9.

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Interrupt mask set.
Writing a 1 to a bit in this register will set the corresponding IMASK bit.

Table 11-9 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5OVFLW0hSets Timer Overflow Event Interrupt Mask.
0h = Writing 0 has no effect
1h = Set interrupt mask
4EV4W0hSets channel4 Event Interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask
3EV3W0hSets channel3 Event Interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask
2EV2W0hSets channel2 Event Interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask
1EV1W0hSets channel1 Event Interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask
0EV0W0hSets channel0 Event Interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask

11.4.8 IMCLR Register (Offset = 5Ch) [Reset = 00000000h]

IMCLR is shown in Table 11-10.

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Interrupt mask clear.
Writing a 1 to a bit in this register will clear the corresponding IMASK bit.

Table 11-10 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5OVFLW0hClears Timer Overflow Event Interrupt Mask.
0h = Writing 0 has no effect
1h = Clear interrupt mask
4EV4W0hClears channel4 Event Interrupt Mask.
0h = Writing 0 has no effect
1h = Clear interrupt mask
3EV3W0hClears channel3 Event Interrupt Mask.
0h = Writing 0 has no effect
1h = Clear interrupt mask
2EV2W0hClears channel2 Event Interrupt Mask.
0h = Writing 0 has no effect
1h = Clear interrupt mask
1EV1W0hClears channel1 Event Interrupt Mask.
0h = Writing 0 has no effect
1h = Clear interrupt mask
0EV0W0hClears channel0 Event Interrupt Mask.
0h = Writing 0 has no effect
1h = Clear interrupt mask

11.4.9 EMU Register (Offset = 60h) [Reset = 00000000h]

EMU is shown in Table 11-11.

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Emulation control.
This register controls the behavior of the IP related to core halted input.

Table 11-11 EMU Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0HALTR/W0hHalt control.
0h = Free run option. The IP ignores the state of the core halted input.
1h = Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary from where it can resume without corruption.

11.4.10 TIME250N Register (Offset = 100h) [Reset = 00000000h]

TIME250N is shown in Table 11-12.

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Systimer Counter Value - 250ns resolution.
This 32-bit value reads out bits [31:0] of the systimer counter. The counter is 34-bit and runs on CLKSVT/12. It maintains a resolution of 250ns with a range of about 17.9m.

Table 11-12 TIME250N Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0h32-bit counter value [31:0]. This will provide a 250ns resolution and a range of 17.9m.

11.4.11 TIME1U Register (Offset = 104h) [Reset = 00000000h]

TIME1U is shown in Table 11-13.

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Systimer Counter Value - 1μs resolution
This 32-bit value reads out bits[33:2] of the systimer counter. The counter is 34-bit and runs on CLKSVT/12. It maintains a resolution of 1us with a range of about 1 h 11m.

Table 11-13 TIME1U Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0h32-bit counter value [33:2]. This will provide a resolution of 1us and a range of 1hr and 11m.

11.4.12 OUT Register (Offset = 108h) [Reset = 00000000h]

OUT is shown in Table 11-14.

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Systimer's channel Output Event Values

Table 11-14 OUT Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4OUT4R/W0hOutput Value of channel 4.
0h = Event did not occur.
1h = Event occured
3OUT3R/W0hOutput Value of channel 3.
0h = Event did not occur.
1h = Event occured
2OUT2R/W0hOutput Value of channel 2.
0h = Event did not occur.
1h = Event occured
1OUT1R/W0hOutput Value of channel 1.
0h = Event did not occur.
1h = Event occured
0OUT0R/W0hOutput Value of channel 0.
0h = Event did not occur.
1h = Event occured

11.4.13 CH0CFG Register (Offset = 10Ch) [Reset = 00000000h]

CH0CFG is shown in Table 11-15.

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Systimer channel 0 configuration.
This channel has configurability for 250ns and 1us based capture and compare operations.

Table 11-15 CH0CFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4RESR/W0hThis bit decides the RESOLUTION of the channel that will be used.
0h = channel Works in Timer's 1us Resolution.
1h = channel Works in Timer's 250ns resolution
3REARMR/W0hWhen Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled
1h = Re arm is enabled
2-1INPR/W0hDecides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function.
0h = Capture on rising edge
1h = Capture on Falling Edge
2h = Capture on both Edge
0MODER/W0hDecides the channel mode.
0h = channel is disabled
1h = channel is in capture mode

11.4.14 CH1CFG Register (Offset = 110h) [Reset = 00000000h]

CH1CFG is shown in Table 11-16.

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Systimer channel 1 configuration.
This channel works in 1us based capture and compare operations.

Table 11-16 CH1CFG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3REARMR/W0hWhen Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled
1h = Re arm is enabled
2-1INPR/W0hDecides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
0h = Capture on rising edge
1h = Capture on Falling Edge
2h = Capture on both Edge
0MODER/W0hDecides the channel mode.
0h = channel is disabled
1h = channel is in capture mode

11.4.15 CH2CFG Register (Offset = 114h) [Reset = 00000000h]

CH2CFG is shown in Table 11-17.

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Systimer channel 2 configuration.
This channel works in 250ns based capture and compare operations.

Table 11-17 CH2CFG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3REARMR/W0hWhen Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled
1h = Re arm is enabled
2-1INPR/W0hDecides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
0h = Capture on rising edge
1h = Capture on Falling Edge
2h = Capture on both Edge
0MODER/W0hDecides the channel mode.
0h = channel is disabled
1h = channel is in capture mode

11.4.16 CH3CFG Register (Offset = 118h) [Reset = 00000000h]

CH3CFG is shown in Table 11-18.

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Systimer channel 3 configuration.
This channel works in 250ns based capture and compare operations.

Table 11-18 CH3CFG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3REARMR/W0hWhen Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled
1h = Re arm is enabled
2-1INPR/W0hDecides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
0h = Capture on rising edge
1h = Capture on Falling Edge
2h = Capture on both Edge
0MODER/W0hDecides the channel mode.
0h = channel is disabled
1h = channel is in capture mode

11.4.17 CH4CFG Register (Offset = 11Ch) [Reset = 00000000h]

CH4CFG is shown in Table 11-19.

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Systimer channel 4 configuration.
This channel works in 250ns based capture and compare operations.

Table 11-19 CH4CFG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3REARMR/W0hWhen Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled
1h = Re arm is enabled
2-1INPR/W0hDecides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
0h = Capture on rising edge
1h = Capture on Falling Edge
2h = Capture on both Edge
0MODER/W0hDecides the channel mode.
0h = channel is disabled
1h = channel is in capture mode

11.4.18 CH0CC Register (Offset = 120h) [Reset = 00000000h]

CH0CC is shown in Table 11-20.

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System Timer channel 0 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.

Table 11-20 CH0CC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.19 CH1CC Register (Offset = 124h) [Reset = 00000000h]

CH1CC is shown in Table 11-21.

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System Timer channel 1 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.

Table 11-21 CH1CC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.20 CH2CC Register (Offset = 128h) [Reset = 00000000h]

CH2CC is shown in Table 11-22.

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System Timer channel 2 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.

Table 11-22 CH2CC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.21 CH3CC Register (Offset = 12Ch) [Reset = 00000000h]

CH3CC is shown in Table 11-23.

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System Timer channel 3 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.

Table 11-23 CH3CC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.22 CH4CC Register (Offset = 130h) [Reset = 00000000h]

CH4CC is shown in Table 11-24.

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System Timer channel 4 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.

Table 11-24 CH4CC Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.23 TIMEBIT Register (Offset = 134h) [Reset = 00000000h]

TIMEBIT is shown in Table 11-25.

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Systimer's Time bit.
This Register will be used to specify which TIME bit is required by LGPT to be forwarded from SYSTIMER.

Table 11-25 TIMEBIT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0VALR/W0hThe corresponding bit will have value '1' rest should be '0'. If more than one bit is asserted, output is "or" of all the bits.
0h = No bit is forwarded to the event fabric.
1h = Bit2 is forwarded to the event fabric.
2h = Bit3 is forwarded to the event fabric.
4h = Bit4 is forwarded to the event fabric.
8h = Bit5 is forwarded to the event fabric.
10h = Bit6 is forwarded to the event fabric.
20h = Bit7 is forwarded to the event fabric.
40h = Bit8 is forwarded to the event fabric.
80h = Bit9 is forwarded to the event fabric.
100h = Bit10 is forwarded to the event fabric.
200h = Bit11 is forwarded to the event fabric.
400h = Bit12 is forwarded to the event fabric.
800h = Bit13 is forwarded to the event fabric.
1000h = Bit14 is forwarded to the event fabric.
2000h = Bit15 is forwarded to the event fabric.
4000h = Bit16 is forwarded to the event fabric.
8000h = Bit17 is forwarded to the event fabric.

11.4.24 STATUS Register (Offset = 140h) [Reset = 00000010h]

STATUS is shown in Table 11-26.

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Systimer status.
This register can be used to read the running status of the timer and to resync the Systimer with RTC.

Table 11-26 STATUS Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4SYNCUPR/W1hThis bit indicates sync status of Systimer with RTC. The bitfield has a reset value of '1', which gets cleared to '0' after the Systimer synchronizes with RTC on the first LFTICK edge. A write to this bit resynchronizes the Systimer with RTC on the next LFTICK edge. A read value of '1' indicates the synchronization is ongoing and a read of '0' indicates the synchronization is done.
3-1RESERVEDR0hReserved
0VALR0h This bit indicates if the system time is initialized and running.
0h = system timer is not running.
1h = system timer is running

11.4.25 ARMSET Register (Offset = 144h) [Reset = 00000000h]

ARMSET is shown in Table 11-27.

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ARMSET
Reading this register gives out the status of the 5 channels.
Channel state UNARMED returns 0.
Channel state CAPTURE or COMPARE returns 1.
A write to ARMSET has for each channel the following effect -
If ARMSTA[x]==0 -> no effect
If ARMSTA[x]==1 and channel x is in CAPTURE state then no effect on the channel
Else, set channel in COMPARE mode using existing CHxVAL value

Table 11-27 ARMSET Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4CH4R/W0hArming channel 4 for either compare or capture operation.
0h = No effect on the channel
1h = if channel 4 is in CAPTURE state then no effect on the channel else it can set channel in COMPARE mode using existing CH4CC.VAL value.
3CH3R/W0hArming channel 3 for either compare or capture operation.
0h = No effect on the channel
1h = if channel 3 is in CAPTURE state then no effect on the channel else it can set channel in COMPARE mode using existing CH3CC.VAL value
2CH2R/W0hArming channel 2 for either compare or capture operation.
0h = No effect on the channel
1h = if channel 2 is in CAPTURE state then no effect on the channel else it can set channel in COMPARE mode using existing CH2CC.VAL value
1CH1R/W0hArming channel 1 for either compare or capture operation.
0h = No effect on the channel
1h = if channel 1 is in CAPTURE state then no effect on the channel else it can Set channel in COMPARE mode using existing CH1CC.VAL value
0CH0R/W0hArming channel 0 for either compare or capture operation.
0h = No effect on the channel
1h = if channel 0 is in CAPTURE state then no effect on the channel else it can set channel in COMPARE mode using existing CH0CC.VAL value

11.4.26 ARMCLR Register (Offset = 148h) [Reset = 00000000h]

ARMCLR is shown in Table 11-28.

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ARMCLR
Read of this register gives out the status of the 5 channels .
Channel state UNARMED returns 0.
Channel state CAPTURE or COMPARE returns 1.
A write to ARMCLR has for each channel the following effect -
If ARMCLR[x]==0 -> no effect.
Else, set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle

Table 11-28 ARMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4CH4R/W0hDisarming channel 4
0h = No effect on the channel
1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle
3CH3R/W0hDisarming channel 3
0h = No effect on the channel
1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle
2CH2R/W0hDisarming channel 2
0h = No effect on the channel
1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle
1CH1R/W0hDisarming channel 1
0h = No effect on the channel
1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle
0CH0R/W0hDisarming channel 0
0h = No effect on the channel
1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle

11.4.27 CH0CCSR Register (Offset = 14Ch) [Reset = 00000000h]

CH0CCSR is shown in Table 11-29.

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Save/restore alias register for channel 0.
A read to this register behaves exactly as a read to CH0CC.
Write to CH0CCSR sets CH0CC.VAL value of register without affecting channel state or configuration

Table 11-29 CH0CCSR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.28 CH1CCSR Register (Offset = 150h) [Reset = 00000000h]

CH1CCSR is shown in Table 11-30.

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Save/restore alias registers channel 1.
A read to CH1CCSR behaves exactly as a read to CH1VAL.
Write to this register sets CH1CC.VAL without affecting channel state or configuration.

Table 11-30 CH1CCSR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.29 CH2CCSR Register (Offset = 154h) [Reset = 00000000h]

CH2CCSR is shown in Table 11-31.

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Save/restore alias registers channel 2.
A read to CH2CCSR behaves exactly as a read to CH2CC
Write to CH2CCSR sets CH2CC.VAL value of register without affecting channel state or configuration

Table 11-31 CH2CCSR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.30 CH3CCSR Register (Offset = 158h) [Reset = 00000000h]

CH3CCSR is shown in Table 11-32.

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Save/restore alias registers channel 3.
A read to CH3CCSR behaves exactly as a read to CH3CC
Write to CH3CCSR sets CH3CC.VAL value of register without affecting channel state or configuration.

Table 11-32 CH3CCSR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value

11.4.31 CH4CCSR Register (Offset = 15Ch) [Reset = 00000000h]

CH4CCSR is shown in Table 11-33.

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Save/restore alias registers channel 4.
A read to CH4CCSR behaves exactly as a read to CH4CC
Write to CH4CCSR sets CH4CC.VAL value of register without affecting channel state or configuration.

Table 11-33 CH4CCSR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCapture/compare value