The purpose of the ADC is to measure
analog signals and convert them to a digital representation with minimal CPU
intervention providing for lower power and greater task integration.
The ADC supports fast 12-, 10-, and
8-bit analog-to-digital conversions. The ADC implements a 12-bit Successive
Approximation Register (SAR) core, sample/conversion mode control, and up to 4
independent conversion-and-control buffers. This means the ADC allows up to 4
independent analog-to-digital converter (ADC) samples to be converted and stored
without any CPU intervention.
ADC features include:
- 1-Msps conversion rate at a resolution of 12 bits when reference is external or
supply (VDDS)
- 200-ksps sampling rate with internal reference
- Full scale ADC operating voltage range
- 12-bit max resolution with
support for 10-bit and 8-bit lower resolution modes
- Sample-and-hold with programmable sampling periods controlled by software or
timers
- Two sampling trigger sources: software trigger and event trigger
- Software-selectable on-chip reference voltage of 1.4V or 2.5V
- Configurable ADC reference
source: VDDS, internal reference (VREF), or external reference (VREF+/-)
- Up to 16 individually
configurable analog input channels
- Internal conversion channels for temperature sensing, supply monitoring, and
analog signal chain (see device-specific data sheet for availability and channel
mapping)
- Configurable ADC clock source
- Different conversion modes:
Single-channel, repeat-single-channel, sequence, repeat-sequence, and software
requested ad-hoc single conversion modes
- Four 16-bit conversion-result
storage registers (MEMRES0:3)
- Support for FIFO and non-FIFO
modes for CPU and µDMA
- Data compaction within FIFO for
32-bit reads
- Window comparator with provision to configure low and high threshold values for
low-power monitoring of input signals from conversion-result registers
- µDMA support with interrupt event
generation on completion of transfer
- Automatic and manual power down schemes
- Unsigned binary and two's complement data format
- 10-bit sample timer with two independent sample time compare registers
- Sample time compare value selection in each memory control register
- Provision to enable window comparator in each memory control register
- Auto-next or trigger-next
configuration for sequence or repeated sequence of channels operation
- Different event sources with single event output
- µDMA trigger logic and interface
to work with µDMA
Figure 17-1 shows the functional block diagram of the ADC peripheral.