SBAA534 March   2022 ADC128S102-SEP , ADC128S102QML-SP , ADS1278-SP , ADS1282-SP , LF411QML-SP , LM101AQML-SP , LM111QML-SP , LM119QML-SP , LM124-SP , LM124AQML-SP , LM136A-2.5QML-SP , LM139-SP , LM139AQML-SP , LM148JAN-SP , LM158QML-SP , LM185-1.2QML-SP , LM185-2.5QML-SP , LM193QML-SP , LM4050QML-SP , LM6172QML-SP , LM7171QML-SP , LMH5401-SP , LMH5485-SEP , LMH5485-SP , LMH6628QML-SP , LMH6702QML-SP , LMH6715QML-SP , LMP2012QML-SP , LMP7704-SP , OPA4277-SP , OPA4H014-SEP , OPA4H199-SEP , THS4304-SP , THS4511-SP , THS4513-SP , TL1431-DIE , TL1431-SP , TLC2201-SP , TLV1704-SEP

 

  1. 1Component and Topology Selection - Finding a Good Starting Point Quickly
  2. 2Verification
    1. 2.1 Detailed Design Procedure – Verification of the Time Domain Response
    2. 2.2 Analysis of Total Noise
    3. 2.3 Linearity or Frequency Response
    4. 2.4 Stability
    5. 2.5 Settling Time
  3. 3Summary

2 Verification

This chapter shows how to verify the example design towards the desired design goals with the help of both the TINA TI Simulator tool and the ANALOG-ENGINEER’S CALCULATOR. The section also shows how to verify that the signal chain performs to the full differential and common-mode input range of the ADC. Then the total noise performance and the linearity are observed to determine if the ENOB target can be met, followed by a stability analysis and verification of the input impedance. Finally, the chapter provides proof that the circuit meets the settling time requirement of the sample and hold capacitor of the ADC.