SBAA637 June   2024 AFE7900 , AFE7901 , AFE7903 , AFE7906 , AFE7950 , AFE7950-SP , AFE7951 , AFE7953 , AFE7954 , AFE7955 , AFE7958

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 SPI Failure During Bring-Up
    1. 2.1 Detail Regarding Chip Readouts
    2. 2.2 Failure and Fix for Chip Read Check
    3. 2.3 Poll Check for SPI Access for PLL Page
    4. 2.4 Failure and Fix for the SPI Poll Check for PLL Page Access
    5. 2.5 Read Check Indicating Status of Fuse Farm Autoload
    6. 2.6 Failure and Fix for Autoload Read Check
  6. 3 Macro Failure Breaking the Bring-Up Flow
    1. 3.1 Read Check for Macro Error and Poll Check for Macro Done
    2. 3.2 Failure and Fix for Macro Error and Poll check for Macro Done
  7. 4 AFE PLL Failure
    1. 4.1 Read Check for PLL Lock
    2. 4.2 Failure and Fix for Read Check of PLL
  8. 5 AFE Internal Sysref Flag Failure
    1. 5.1 Read Check Status of Sysref Flag Bit
    2. 5.2 Failure and Fix for Read Check Status of Sysref Flag Bit
  9. 6 JESD Link Check Failure
    1. 6.1 Multiple Read Checks Indicating Status of JESD Linkup
    2. 6.2 Failure and Fix for JESD Error
  10. 7 Validating Serdes and JESD Link using CAPI
    1. 7.1 Useful Serdes Debug CAPIs
    2. 7.2 Useful JESD Debug CAPIs
  11. 8 TX Chain Validation
  12. 9 RX Chain Validation
  13. 10Device Health
  14. 11Summary
  15. 12References

6.1 Multiple Read Checks Indicating Status of JESD Linkup

  1. JESD linkup is done at the end of AFE bring-up. We have multiple check points for JESD linkup status of AFE. During the bring-up flow serdes is already linked during the AFE bring-up. Do make sure the FPGA/ ASIC STX is transmitting some data so that the CDR of AFE SRX can adapt and achieve serdes linkup between AFE and FPGA/ASIC.

    During JESD Linkup we check for Serdes and JESD linkup and error status. Below is list read check done during bring-up.

    1. SPIReadCheck 0118,0,7,00 #Below is the definition of error indicated for 0x118

      [3:0] = TIED to 0

      [4] = JESD shorttest alarm

      [5] = TIED to 0

      [6] = serdesab_pll_loss_of_lock

      [7] = serdescd_pll_loss_of_lock

    2. SPIReadCheck 0119,0,7,00

      [0] = SRX1 LOS indicator

      [1] = SRX2 LOS indicator

      [2] = SRX3 LOS indicator

      [3] = SRX4 LOS indicator

      [4] = SRX1 Serdes-FIFO error

      [5] = SRX2 Serdes-FIFO error

      [6] = SRX3 Serdes-FIFO error

      [7] = SRX4 Serdes-FIFO error

    3. SPIReadCheck 011a,0,7,00

      TIED to 0

    4. SPIReadCheck 011b,0,7,00

      [3:0] = TIED to 0

      [4] = JESDB: Lane0 Frame-Sync error (Ctrl-K in middle of data) JESDC: Lane0 Fixed ones error

      [5] = JESDB: Lane1 Frame-Sync error (Ctrl-K in middle of data) JESDC: Lane1 Fixed ones error

      [6] = JESDB: Lane2 Frame-Sync error (Ctrl-K in middle of data) JESDC: Lane2 Fixed ones error

      [7] = JESDB: Lane3 Frame-Sync error (Ctrl-K in middle of data) JESDC: Lane3 Fixed ones error

    5. SPIReadCheck 011c,0,7,00

      Below is lane error for JESD 204B protocol for lane 0:

      bit7 = JESDB: multiframe alignment error

      bit6 = JESDB: frame alignment error

      bit5 = JESDB: link configuration error

      bit4 = JESDB: elastic buffer overflow (bad RBD value)

      bit3 = JESDB: elastic buffer match error. The first non-/K/ does not match 'match_ctrl' and 'match_data' programmed values

      bit2 = JESDB: code synchronization error

      bit1 = JESDB: 8b/10b not-in-table code error

      bit0 = JESDB: 8b/10b disparity error

      If we use JESD 204C protocol, below is the lane error mapped to for lane 0:

      bit7 = JESDC: EoEMB alignment error

      bit6 = JESDC: EoMB alignment error

      bit5 = JESDC: cmd-data in crc mode not matching with spi register bits

      bit4 = JESDC: elastic buffer overflow (bad RBD value)

      bit3 = JESDC: TIED to 0. bit2 = JESDC: extended multiblock alignment error

      bit1 = JESDC: sync-header invalid error ('11' or '00' received in expected sync header location)

      bit0 = JESDC: sync-header CRC error

    6. SPIReadCheck 011e,0,7,00

      Same as above lane error mapping for JESD lane 1

    7. SPIReadCheck 011d,0,7,00

      Same as above lane error mapping for JESD lane 2

    8. SPIReadCheck 011c,0,7,00

      Same as above lane error mapping for JESD lane 2

    9. SPIReadCheck 00ee,0,3,0f

      JESDB: comma_align_lock_lane[0:3]monitor_flag

      JESDC: sync_header_align_lock_lane[0:3]monitor_flag

    10. SPIReadCheck 00a2,0,7,aa

      JESDB: CS_STATE value

      JESDC: EMB_STATE value

      bits(1:0) = Lane0

      bits(3:2) = Lane1

      bits(5:4) = Lane2

      bits(7:6) = Lane3

      For stable link, the bits for each lane enabled can read as "10"

    11. SPIReadCheck 00a4,0,7,55

      JESDB: FS_STATE value

      bits(1:0) = Lane0

      bits(3:2) = Lane1

      bits(5:4) = Lane2

      bits(7:6) = Lane3

      For stable link, the bits for each lane enabled can read as "01"

    12. SPIReadCheck 00a6,0,7,FF

      JESDB/C: ELASTIC_BUFFER_STATE value

      bits(1:0) = Lane0

      bits(3:2) = Lane1

      bits(5:4) = Lane2

      bits(7:6) = Lane3

      For stable link, the bits for each lane enabled can read as "11".

Same registers are read check for second instance of JESD, that is JESD Lane4, 5, 6, 7