SBAA702 July   2025 AFE8190

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Fast Bring-up on AFE81xx
  6. 3 Fast Bring-up Sequence
  7. 4 Input Parameter Constraint
  8. 5 Calibration Memory
  9. 6 Fuse Blow Requirement
  10. 7 Drifts and Aging
  11. 8 Device Bring-up Time
  12. 9 Summary
  13. 10References

4 Input Parameter Constraint

Input parameters, including input clock frequency, ADC Rate, DAC Rate, NCO frequencies, SERDES lane rate, interface rate has to be fixed before doing the fuse blow. PLL calibration values change if input clock frequency changes. The serdes calibration change with lane rate and link configuration. The serdes automatically adjusts timings designed for timing margins, so this adapts to any minor variations (within limits). However, in modular system, the AFE and FPGAs can be on different boards. If backend board changes (from calibrated board) with different link equalization, there can be need for JESD link re-equalization.