SBAU251B July   2017  – February 2023 ADS8331 , ADS8332

 

  1.   ADS8332EVMV2-PDK User's Guide
  2.   Trademarks
  3. 1Overview
    1. 1.1 ADS8332EVMV2-PDK Features
    2. 1.2 ADS8332EVMV2 Features
  4. 2EVM Analog Interface
    1. 2.1 ADS8332EVMV2 Onboard Reference
  5. 3Digital Interfaces
    1. 3.1 ADS8332 Digital Interface
  6. 4Power Supplies
  7. 5ADS8332EVMV2-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface (GUI) Software Installation
  8. 6ADS8332EVMV2-PDK Operation
    1. 6.1 EVM GUI Global Settings for ADC Control
    2. 6.2 Time Domain Display Tool
    3. 6.3 Spectral Analysis Tool
    4. 6.4 Histogram Tool
    5. 6.5 Linearity Analysis Tool
    6. 6.6 Input Amplifier Configurations
  9. 7Bill of Materials, PCB Layout, and Schematics
    1. 7.1 Bill of Materials
    2. 7.2 PCB Layout
    3. 7.3 Schematics
  10. 8Revision History

4 Power Supplies

The ADS8332 ADC analog supply (AVDD) is provided by a low-noise linear regulator (TPS7A4700). The regulator uses a 5.5-V supply out of a switching regulator from the PHI controller to generate a quiet and stable 5.2-V supply output. The 3.3-V supply to the digital supply of the ADS8332 is provided directly by an LDO from the PHI controller. The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed close to that component. Additionally, the EVM layout uses thick traces or large copper filled areas where possible between bypass capacitors and their loads to minimize inductance along the load current path.

When using the ADS8332EVMV2 in conjunction with the PHI controller, the PHI controller supplies the AVDD and DVDD supply. Do not supply external power supply voltages.