SBAU441B March   2024  – October 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications and Device Information
  8. 2Hardware
    1. 2.1 Board Overview
    2. 2.2 Required Equipment
    3. 2.3 Hardware Setup
  9. 3Software
    1. 3.1 Required Software
    2. 3.2 Software Setup
    3. 3.3 Using the GUI
  10. 4Hardware Design Files
  11. 5Additional Information
    1. 5.1 Trademarks
    2. 5.2 References
  12. 6Revision History

2.3 Hardware Setup

  1. Make sure jumper J2 on the TSWDC155EVM is connected across pins 1-2
    ADC3669EVM TSWDC155EVM Jumper Configuration Figure 2-2 TSWDC155EVM Jumper Configuration
  2. Make sure the 12V Power switch on the ADC3669EVM is switched to JACK
  3. Make sure the Comms switch on the ADC3669EVM is switched to USB
  4. Connect the ADC3669EVM to the TSWDC155EVM by the FMC connectors
  5. Connect the mini-USB connector on the ADC3669EVM to the PC using the mini-USB cable provided in the EVM kit
  6. Connect the 12V 1A power supply to the barrel jack of the ADC3669EVM
  7. Using the included mini-USB cable, connect the PC to the JTAG dongle and connect the JTAG dongle to the JTAG header J7 on the TSWDC155EVM
  8. Using the included USB-C® cable, connect the PC to the USB-C port J8 on the TSWDC155EVM
  9. Using an SMA cable and an inline 500MHz band-pass filter, connect the signal generator to the SMA connector labeled CLK on the ADC3669EVM. Set the output signal frequency of the signal generator to 500MHz and the signal amplitude to +10dBm
  10. By default, the EVM is configured to take a single-ended input, so analog inputs are applied to connectors AINp and BINp on the ADC3669EVM. Using an SMA cable and an inline 10MHz band-pass filter, apply an input signal to Channel A by connecting the signal generator output to the SMA connector on the ADC3669EVM labeled AINp. Set the output signal frequency of the signal generator to 10MHz and the signal amplitude to roughly +10dBm
Note: Reference lock all signal generators for clock, analog input, and DCLK using the 10MHz REF on the back of the signal generators.

Figure 2-3 shows the ADC3669EVM setup.

ADC3669EVM Assembled Setup of the ADC3669EVMFigure 2-3 Assembled Setup of the ADC3669EVM