SBAU484 February   2025 AFE7728D , AFE7768D , AFE7769D

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware and Software Setup
    1. 2.1 Hardware Setup
    2. 2.2 Software Setup
    3. 2.3 Test Cases
      1. 2.3.1 Initial Bringup for All Test Cases
        1. 2.3.1.1 Test Case 1: Generate Sinusoidal tx_data From NCO @ 5MHz
        2. 2.3.1.2 Test case 2: Generate Sinusoidal tx_data From NCO @ 20MHz
        3. 2.3.1.3 Test Case 3: Connect Signal Generator Output Port to RX of the AFE7769DEVM (at output power, -13dBm)
        4. 2.3.1.4 Test Case 4: Connect Signal Generator Output Port to RX of the AFE7769DEVM (at output power, -23dBm)

2.3.1 Initial Bringup for All Test Cases

  1. Launch AFE77xxD Latte GUI.
  2. An initial window pops up with the device setup information; verify the window has the exact same settings as shown in Figure 2-2.
    Initial Setup, AFE77xxD Figure 2-2 Initial Setup, AFE77xxD
  3. Navigate to the AFE-Configuration tab on the left-hand side of the application, and “Load” the “AFE77xxD_8.1_9.1.xlsx” file.
  4. Ensure the following message appears in the Log window once the configuration file is loaded:
    1. Loaded Configuration: ‘AFE77xxD_8.1_9.1.xlsx’
    2. Refreshed GUI.
  5. Do not click "Run Device Bringup" in Latte yet.
  6. Keep Latte open; launch Quartus Programmer.
  7. Click “Hardware Setup” at the top of the pane, and ensure “USB-BlasterII [USB-1]” is selected.
    Hardware Setup Window Figure 2-3 Hardware Setup Window
  8. Click “Auto Detect” and a window of different FPGA names will pop up. Select 10AS066N2, and click “OK”.
    Auto Detect Window Figure 2-4 Auto Detect Window
  9. In the middle pane, a four-component block diagram will appear. Referencing the order of the blocks in the “File” column, select the third one (also known as the “1_BIT_TAP” block) and click “Delete”.
    Remove "1_BIT_TAP" Figure 2-5 Remove "1_BIT_TAP"
  10. Next, select the first block in the same “File” column and click “Change File”.
    Change "10AS066N2" Figure 2-6 Change "10AS066N2"
  11. In File Explorer, select the “j204b_test.sof” file and click “Open”.
    Insert .sof File Figure 2-7 Insert .sof File
  12. Verify the block diagram looks exactly like the following, especially from an order perspective.
    Updated Block Diagram Figure 2-8 Updated Block Diagram
  13. Navigate back to Latte and click "Run Device Bringup".
  14. Monitor the Log window. Once you see the “LMK Configured” message, navigate back to Quartus Programmer and click “Start”.
    "LMK Configured" Indicator Figure 2-9 "LMK Configured" Indicator
  15. In Quartus Programmer, monitor the Progress bar on the top right corner of the window. It will progress to “100% (Successful)” within a minute.
  16. Return to Latte GUI and monitor Device Bringup until complete. This is indicated by the final message in the Log window displaying “AFE configuration Complete”, followed by a record of the number of errors and warnings.
  17. At the end of bringup, the Log window notifies the user of only two errors (no warnings), which includes “FPGA Reset device not found” twice. This is normal and nothing to worry about as Latte currently only recognizes the TSW14J58EVM, a TI FPGA, by name.