SBAU484 February   2025 AFE7728D , AFE7768D , AFE7769D

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware and Software Setup
    1. 2.1 Hardware Setup
    2. 2.2 Software Setup
    3. 2.3 Test Cases
      1. 2.3.1 Initial Bringup for All Test Cases
        1. 2.3.1.1 Test Case 1: Generate Sinusoidal tx_data From NCO @ 5MHz
        2. 2.3.1.2 Test case 2: Generate Sinusoidal tx_data From NCO @ 20MHz
        3. 2.3.1.3 Test Case 3: Connect Signal Generator Output Port to RX of the AFE7769DEVM (at output power, -13dBm)
        4. 2.3.1.4 Test Case 4: Connect Signal Generator Output Port to RX of the AFE7769DEVM (at output power, -23dBm)

2.1 Hardware Setup

This section discusses the initial setup of the test environment, as well as the necessary power connections.

  1. Mount the FMC+ connector of the AFE7769DEVM to the receiving part on the Arria 10 FPGA (labeled J19), as shown in Figure 2-1.
    AFE7769DEVM and Arria 10 FPGA Figure 2-1 AFE7769DEVM and Arria 10 FPGA
  2. Ensure the following connections are made to the necessary power supplies/ports, and that the Arria 10 is switched on, as shown above. The switch can be found in the bottom-right corner of the above figure.
    1. USB-C cable: connected to PC used to launch Latte GUI.
    2. AFE7769DEVM Power cable: connected to a power supply @ 5.5V
    3. Ethernet cable: connected to Ethernet port
    4. USB Blaster cable: connected to PC used to launch Quartus Programmer and SignalTap
    5. Arria 10 Power cable: connected to safe power outlet

For all other hardware integrations for the Arria 10, see the Intel® Arria® 10 SX SoC Development Kit.