SBOS123A December 1999 – December 2025 INA148
PRODUCTION DATA
At TA = +25°C, VS = ±15V, RL = 10kΩ to common, and VREF = 0V, and all chip site origin (CSO), (unless otherwise noted)



Figure 5-9 Voltage Noise (RTI) 0.1Hz
to 10Hz
Figure 5-13 Large-Signal Step Response
vs Temperature
Figure 5-17 Large-Signal Step Response
(RL = 10kΩ, CL = 10pF)
Figure 5-25 Offset Voltage Production
Distribution
Figure 5-27 Offset Voltage Drift
Production Distribution
Figure 5-29 Gain Drift Production
Distribution
Figure 5-8 Input Voltage Noise
Spectral Density
Figure 5-10 Quiescent Current vs
Temperature


Figure 5-24 Offset Voltage Production
Distribution
Figure 5-26 Offset Voltage Drift
Production Distribution
Figure 5-28 Gain Drift Production
Distribution