SBOS776D March   2016  – September 2026 INA3221-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Basic ADC Functions
      2. 7.3.2 Alert Monitoring
        1. 7.3.2.1 Critical Alert
          1. 7.3.2.1.1 Summation Control Function
        2. 7.3.2.2 Warning Alert
        3. 7.3.2.3 Power-Valid Alert
        4. 7.3.2.4 Timing-Control Alert
        5. 7.3.2.5 Default Settings
      3. 7.3.3 Software Reset
    4. 7.4 Device Functional Modes
      1. 7.4.1 Averaging Function
      2. 7.4.2 Multiple Channel Monitoring
        1. 7.4.2.1 Channel Configuration
        2. 7.4.2.2 Averaging and Conversion-Time Considerations
      3. 7.4.3 Filtering and Input Considerations
    5. 7.5 Programming
      1. 7.5.1 Bus Overview
        1. 7.5.1.1 Serial Bus Address
        2. 7.5.1.2 Serial Interface
      2. 7.5.2 Writing To and Reading From the INA3221-Q1
        1. 7.5.2.1 High-Speed I2C Mode
      3. 7.5.3 SMBus Alert Response
  9. 8 Register Maps
    1. 8.1 Summary of Register Set
    2. 8.2 Register Descriptions
      1. 8.2.1  Configuration Register (address = 00h) [reset = 7127h]
      2. 8.2.2  Channel-1 Shunt-Voltage Register (address = 01h), [reset = 00h]
      3. 8.2.3  Channel-1 Bus-Voltage Register (address = 02h) [reset = 00h]
      4. 8.2.4  Channel-2 Shunt-Voltage Register (address = 03h) [reset = 00h]
      5. 8.2.5  Channel-2 Bus-Voltage Register (address = 04h) [reset = 00h]
      6. 8.2.6  Channel-3 Shunt-Voltage Register (address = 05h) [reset = 00h]
      7. 8.2.7  Channel-3 Bus-Voltage Register (address = 06h) [reset = 00h]
      8. 8.2.8  Channel-1 Critical-Alert Limit Register (address = 07h) [reset = 7FF8h]
      9. 8.2.9  Warning-Alert Channel-1 Limit Register (address = 08h) [reset = 7FF8h]
      10. 8.2.10 Channel-2 Critical-Alert Limit Register (address = 09h) [reset = 7FF8h]
      11. 8.2.11 Channel-2 Warning-Alert Limit Register (address = 0Ah) [reset = 7FF8h]
      12. 8.2.12 Channel-3 Critical-Alert Limit Register (address = 0Bh) [reset = 7FF8h]
      13. 8.2.13 Channel-3 Warning-Alert Limit Register (address = 0Ch) [reset = 7FF8h]
      14. 8.2.14 Shunt-Voltage Sum Register (address = 0Dh) [reset = 00h]
      15. 8.2.15 Shunt-Voltage Sum-Limit Register (address = 0Eh) [reset = 7FFEh]
      16. 8.2.16 Mask/Enable Register (address = 0Fh) [reset = 0002h]
      17. 8.2.17 Power-valid Upper-limit Register (address = 10h) [reset = 2710h]
      18. 8.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]
      19. 8.2.19 Manufacturer ID Register (address = FEh) [reset = 5449h]
      20. 8.2.20 Die ID Register (address = FFh) [reset = 3220]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8 Register Maps

The INA3221-Q1 uses a bank of registers for holding configuration settings, measurement results, minimum and maximum limits, and status information. Table 8-1 summarizes the INA3221-Q1 registers; see the Functional Block Diagram section for an illustration of the registers.