SBOSAC3B July   2023  – August 2025 INA745A , INA745B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements (I2C)
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Integrated Shunt Resistor
      2. 6.3.2 Safe Operating Area
      3. 6.3.3 Versatile Measurement Capability
      4. 6.3.4 Internal Measurement and Calculation Engine
      5. 6.3.5 High-Precision Delta-Sigma ADC
        1. 6.3.5.1 Low Latency Digital Filter
        2. 6.3.5.2 Flexible Conversion Times and Averaging
      6. 6.3.6 Integrated Precision Oscillator
      7. 6.3.7 Multi-Alert Monitoring and Fault Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Power-On Reset
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 Writing to and Reading Through the I2C Serial Interface
        2. 6.5.1.2 High-Speed I2C Mode
        3. 6.5.1.3 SMBus Alert Response
  8. 7 Register Maps
    1. 7.1 INA745x Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 ADC Output Data Rate and Noise Performance
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Configure the Device
        2. 8.2.2.2 Set Desired Fault Thresholds
        3. 8.2.2.3 Calculate Returned Values
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at TA = 25 °C, VS = 3.3 V, ISENSE  = 0 A, VCM = VIN– = VBUS= 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
CMRR Common-mode rejection –0.1 V < VCM < 40 V,
TA = –40°C to +125°C		 A devices ±25 ±60 µA/V
B devices ±0.5 ±1.25 mA/V
Ios Input offset current TCT > 280 µs A devices ±0.9 ±6.25 mA
B devices ±7.5 ±62.5 mA
dVos/dT Input offset current drift TA = –40°C to +125°C ±5 ±30 µA/°C
PSRR Input offset current vs power supply VS = 2.7 V to 5.5 V, TA = –40°C to +125°C ±0.1 ±4 mA/V
Vos_bus VBUS offset voltage VBUS = 20 mV ±2 ±5 mV
dVos/dT VBUS offset voltage drift TA = –40°C to +125°C A devices ±8 ±40 µV/°C
B devices ±20 ±100 µV/°C
PSRR VBUS offset voltage vs power supply VS = 2.7 V to 5.5 V ±1.1 ±4 mV/V
DC ACCURACY
GSERR System current sense gain error ISENSE = –25A to +25 A, VCM = 12 V A devices ±0.1 ±0.75 %
GSERR System current sense gain error ISENSE = –25A to +25 A, VCM = 12 V B devices ±0.1 ±1.25 %
GS_DRFT System current sense gain error drift –40°C ≤ TA ≤ 125°C ±75 ppm/°C
GBERR VBUS voltage gain error VBUS = 0 V to 40 V A devices ±0.01 ±0.075 %
VBUS = 0 V to 40 V,
–40°C ≤ TA ≤ 125°C		 ±0.01 ±0.35 %
VBUS = 0 V to 40 V B devices ±0.01 ±0.3 %
VBUS = 0 V to 40 V,
–40°C ≤ TA ≤ 125°C		 ±0.01 ±0.8 %
GB_DRFT VBUS voltage gain error drift –40°C ≤ TA ≤ 125°C A devices ±25 ppm/°C
B devices ±50 ppm/°C
ZBUS VBUS pin input impedance  Device enabled with active conversions 1 MΩ
PTME Power total measurement error (TME) TA = 25°C, at full scale A devices ±0.9 %
B devices ±1.6 %
ETME Energy and charge TME TA = 25°C, at full scale power A devices ±1.4 %
B devices ±2.1 %
ADC resolution 16 Bits
1 LSB step size Current 1.2 mA
Bus voltage 3.125 mV
Temperature 125 m°C
Power 240 µW
Energy 3.84 mJ
Charge 75 µC
TCT ADC conversion-time(1) Conversion time field = 0h  50 µs
Conversion time field = 1h  84
Conversion time field = 2h  150
Conversion time field = 3h  280
Conversion time field = 4h  540
Conversion time field = 5h 1052
Conversion time field = 6h 2074
Conversion time field = 7h  4120
INL Integral Non-Linearity Bus voltage measurement ±2 m%
DNL Differential Non-Linearity Bus voltage measurement 0.2 LSB
CLOCK SOURCE
FOSC Internal oscillator frequency 1 MHz
OSCTOL Internal oscillator frequency tolerance TA = 25°C ±0.5 %
TA = –40°C to +125°C ±1 %
TEMPERATURE SENSOR
Measurement range –40 +150 °C
Temperature accuracy TA = 25°C ±0.15 ±1.5 °C
TA= –40°C to +125°C ±0.2 ±2.5 °C
INTEGRATED SHUNT
Internal kelvin resistance SH+ to SH–, TA = 25°C 800 µΩ
Pin to pin package resistance IS+ to IS–, TA = 25°C 800 1000 1300 µΩ
Maximum continuous current –40°C ≤ TA ≤ 125°C ±25 A
Short time overload change(2) ISENSE = 50 A for 5 seconds ±0.003 %
Change due to temperature cycling –65°C ≤ TA ≤ 150°C, 500 cycles ±0.05 %
Resistance change to solder heat 260°C solder, 10 s ±0.1 %
High temperature exposure change 1000 hours, TA = 150°C ±0.015 %
POWER SUPPLY
VS Supply voltage 2.7 5.5 V
VPOR POR Voltage Level Supply rising 1.26 V
IQ Quiescent current ISENSE = 0 V 640 750 µA
ISENSE = 0 V, TA = –40°C to +125°C 1 mA
IQSD Quiescent current, shutdown Shutdown mode 2.8 5 µA
TPOR Device start-up time Power-up (NPOR) 300 µs
From shutdown mode 60
DIGITAL INPUT / OUTPUT
VIH Logic input level, high SDA, SCL 1.2 5.5 V
VIL Logic input level, low GND 0.4 V
VOL Logic output level, low IOL = 3 mA GND 0.4 V
IIO_LEAK Digital leakage input current 0 ≤ VIN ≤ VS –1 1 µA
(1) Subject to oscillator accuracy and drift
(2) Tested on device EVM, see Section 6.3.2.