SBVS263B July   2017  – June 2025 TPS7A39

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Start-Up Characteristics
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Voltage Regulation
        1. 6.3.1.1 DC Regulation
        2. 6.3.1.2 AC and Transient Response
      2. 6.3.2 User-Settable Buffered Reference
      3. 6.3.3 Active Discharge
      4. 6.3.4 System Start-Up Controls
        1. 6.3.4.1 Start-Up Tracking
        2. 6.3.4.2 Sequencing
          1. 6.3.4.2.1 Enable (EN)
          2. 6.3.4.2.2 Undervoltage Lockout (UVLO) Control
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Setting the Output Voltages on Adjustable Devices
      2. 7.1.2  Capacitor Recommendations
      3. 7.1.3  Input and Output Capacitor (CINx and COUTx)
      4. 7.1.4  Feed-Forward Capacitor (CFFx)
      5. 7.1.5  Noise-Reduction and Soft-Start Capacitor (CNR/SS)
      6. 7.1.6  Buffered Reference Voltage
      7. 7.1.7  Overriding Internal Reference
      8. 7.1.8  Start-Up
        1. 7.1.8.1 Soft-Start Control (NR/SS)
          1. 7.1.8.1.1 In-Rush Current
        2. 7.1.8.2 Undervoltage Lockout (UVLOx) Control
      9. 7.1.9  AC and Transient Performance
        1. 7.1.9.1 Power-Supply Rejection Ratio (PSRR)
        2. 7.1.9.2 Channel-to-Channel Output Isolation and Crosstalk
        3. 7.1.9.3 Output Voltage Noise
        4. 7.1.9.4 Optimizing Noise and PSRR
        5. 7.1.9.5 Load Transient Response
      10. 7.1.10 DC Performance
        1. 7.1.10.1 Output Voltage Accuracy (VOUT x)
        2. 7.1.10.2 Dropout Voltage (VDO)
      11. 7.1.11 Reverse Current
      12. 7.1.12 Power Dissipation (PD)
        1. 7.1.12.1 Estimating Junction Temperature
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1: Single-Ended to Differential Isolated Supply
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Switcher Choice
          2. 7.2.1.2.2 Full Bridge Rectifier With Center-Tapped Transformer
          3. 7.2.1.2.3 Total Solution Efficiency
          4. 7.2.1.2.4 Feedback Resistor Selection
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2: Getting the Full Range of a SAR ADC
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Detailed Design Description
          1. 7.2.2.3.1 Regulation of –0.2V
          2. 7.2.2.3.2 Feedback Resistor Selection
        4. 7.2.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.4.1.2 Package Mounting
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1.9.3 Output Voltage Noise

The TPS7A39 is designed for system applications where minimizing noise on the power-supply rail is critical to system performance. For example, the TPS7A39 can be used in a phase-locked loop (PLL)-based clocking circuit that can be used for minimum phase noise, or in test and measurement systems where even small power-supply noise fluctuations reduce system dynamic range.

LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This noise is the sum of various types of noise (such as shot noise associated with current-through-pin junctions, thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise and dominates at lower frequencies as a function of 1/f). Figure 7-4 shows a simplified output voltage noise density plot versus frequency.

TPS7A39 Output Voltage Noise DiagramFigure 7-4 Output Voltage Noise Diagram

For further details, see the How to Measure LDO Noise white paper.