SBVS324B June   2017  – September 2026 TPS7A90

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage (VDO)
      3. 6.3.3 Output Voltage Accuracy
      4. 6.3.4 High Power-Supply Rejection Ratio (PSRR)
      5. 6.3.5 Low Output Noise
      6. 6.3.6 Output Soft-Start Control
      7. 6.3.7 Power-Good Function
      8. 6.3.8 Internal Protection Circuitry
        1. 6.3.8.1 Undervoltage Lockout (UVLO)
        2. 6.3.8.2 Internal Current Limit (ICL)
        3. 6.3.8.3 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Output
      2. 7.1.2 Start-Up
        1. 7.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 7.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
          1. 7.1.2.2.1 Noise Reduction
          2. 7.1.2.2.2 Soft-Start and In-Rush Current
      3. 7.1.3 Capacitor Recommendation
        1. 7.1.3.1 Input and Output Capacitor Requirements (CIN and COUT)
          1. 7.1.3.1.1 Load-Step Transient Response
        2. 7.1.3.2 Feed-Forward Capacitor (CFF)
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 SPICE Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.4 High Power-Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO control loop rejects noise from the input source to make the dc output voltage as noise-free as possible across the frequency spectrum (usually measured from 10Hz to 10MHz). Even though PSRR is a loss in noise signal amplitude, the PSRR curves in Section 5.6 are shown as positive values in decibels (dB) for convenience. Equation 2 shows the PSRR calculation as a function of frequency where input noise voltage (VIN[f]) and output noise voltage (VOUT[f]) are the amplitudes of the respective sinusoidal signals.

Equation 2. PSRR (dB) = 20 log 10 ( V IN ( f ) V OUT ( f ) )

Noise that couples from the input to the internal reference voltage is a primary contributor to reduced PSRR performance. TI recommends using a noise-reduction capacitor to filter unwanted noise from the input voltage, which creates a low-pass filter with an internal resistor to improve PSRR performance at lower frequencies.

LDOs are often employed not only as a step-down regulators, but also to provide exceptionally clean power rails for noise-sensitive components. This usage is especially true for the TPS7A90, which features a remarkable circuit to boost the PSRR from 200kHz to 1MHz. This boost circuit helps further filter switching noise from switching-regulators that operate in this region; see Section 5.6. To achieve the maximum benefit of this PSRR boost circuit, TI recommends using a capacitor with a minimum impedance in the from 100kHz to 1MHz band.