SCAS847 Data sheet

SCAS847J July 2007 – June 2025 CDCE925 , CDCEL925

PRODUCTION DATA

5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
I_DD	Supply current (see Figure 5-1)	All outputs off, f_CLK = 27MHz, f_VCO = 135MHz, f_OUT = 27MHz	All PLLS on		20		mA
I_DD	Supply current (see Figure 5-1)		Per PLL		9		mA
I_DDOUT	Supply current (see Figure 5-2 and Figure 5-3)	No load, all outputs on, f_OUT = 27MHz	CDCE925, V_DDOUT = 3.3V		2		mA
I_DDOUT	Supply current (see Figure 5-2 and Figure 5-3)	No load, all outputs on, f_OUT = 27MHz	CDCEL925, V_DDOUT = 1.8V		1		mA
I_DDPD	Power-down current. Every circuit powered down except SDA/SCL	f_IN = 0MHz, V_DD = 1.9V			30		µA
V_PUC	Supply voltage V_DD threshold for power-up control circuit			0.85		1.45	V
f_VCO	VCO frequency range of PLL			80		230	MHz
f_OUT	LVCMOS output frequency	CDCEx925 V_DDOUT = 1.8V		230			MHz
LVCMOS
V_IK	LVCMOS input voltage	V_DD = 1.7V, I_S = –18mA				–1.2	V
I_I	LVCMOS input current	V_I = 0V or V_DD, V_DD = 1.9V				±5	µA
I_IH	LVCMOS input current for S0/S1/S2	V_I = V_DD, V_DD = 1.9V				5	µA
I_IL	LVCMOS Input current for S0/S1/S2	V_I = 0V, V_DD = 1.9V				–4	µA
C_I	Input capacitance at Xin/Clk	V_IClk = 0V or V_DD			6		pF
	Input capacitance at Xout	V_IXout = 0V or V_DD			2
	Input capacitance at S0/S1/S2	V_IS = 0V or V_DD			3
CDCE925 – LVCMOS FOR V_DDOUT = 3.3V
V_OH	LVCMOS high-level output voltage	V_DDOUT = 3V, I_OH = –0.1mA		2.9			V
		V_DDOUT = 3V, I_OH = –8mA		2.4
		V_DDOUT = 3V, I_OH = –12mA		2.2
V_OL	LVCMOS low-level output voltage	V_DDOUT = 3V, I_OL = 0.1mA				0.1	V
		V_DDOUT = 3V, I_OL = 8mA				0.5
		V_DDOUT = 3V, I_OL = 12mA				0.8
t_PLH, t_PHL	Propagation delay	All PLL bypass			3.2		ns
t_r/t_f	Rise and fall time	V_DDOUT = 3.3V (20%–80%)			0.6		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	1PLL switching, Y2-to-Y3			50	70	ps
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾⁽³⁾	2PLL switching, Y2-to-Y5			90	130	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	1PLL switching, Y2-to-Y3			60	100	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	2PLL switching, Y2-to-Y5			100	160	ps
t_sk(o)	Output skew ⁽⁴⁾	f_OUT = 50MHz, Y1-to-Y3				70	ps
t_sk(o)	Output skew ⁽⁴⁾	f_OUT = 50MHz, Y2-to-Y5				150	ps
odc	Output duty cycle ⁽⁵⁾	f_VCO = 100MHz, Pdiv = 1		45%		55%
CDCE925 – LVCMOS FOR V_DDOUT = 2.5V
V_OH	LVCMOS high-level output voltage	V_DDOUT = 2.3V, I_OH = –0.1mA		2.2			V
		V_DDOUT = 2.3V, I_OH = –6mA		1.7
		V_DDOUT = 2.3V, I_OH = –10mA		1.6
V_OL	LVCMOS low-level output voltage	V_DDOUT = 2.3V, I_OL = 0.1mA				0.1	V
		V_DDOUT = 2.3V, I_OL = 6mA				0.5
		V_DDOUT = 2.3V, I_OL = 10mA				0.7
t_PLH, t_PHL	Propagation delay	All PLL bypass			3.6		ns
t_r/t_f	Rise and fall time	V_DDOUT = 2.5V (20%–80%)			0.8		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾ ⁽³⁾	1PLL switching, Y2-to-Y3			50	70	ps
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾ ⁽³⁾	2PLL switching, Y2-to-Y5			90	130	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	1PLL switching, Y2-to-Y3			60	100	ps
t_jit(per)	Peak-to-peak period jitter⁽³⁾	2PLL switching, Y2-to-Y5			100	160	ps
t_sk(o)	Output skew⁽⁴⁾	f_OUT = 50MHz, Y1-to-Y3				70	ps
t_sk(o)	Output skew⁽⁴⁾	f_OUT = 50MHz, Y2-to-Y5				150	ps
odc	Output duty cycle⁽⁵⁾	f_VCO = 100MHz, Pdiv = 1		45%		55%
CDCEL925 – LVCMOS FOR V_DDOUT = 1.8V
V_OH	LVCMOS high-level output voltage	V_DDOUT = 1.7V, I_OH = –0.1mA		1.6			V
		V_DDOUT = 1.7V, I_OH = –4mA		1.4
		V_DDOUT = 1.7V, I_OH = –8mA		1.1
V_OL	LVCMOS low-level output voltage	V_DDOUT = 1.7V, I_OL = 0.1mA				0.1	V
		V_DDOUT = 1.7V, I_OL = 4mA				0.3
		V_DDOUT = 1.7V, I_OL = 8mA				0.6
t_PLH, t_PHL	Propagation delay	All PLL bypass			2.6		ns
t_r/t_f	Rise and fall time	V_DDOUT = 1.8V (20%–80%)			0.7		ns
t_jit(cc)	Cycle-to-cycle jitter ⁽²⁾ ⁽³⁾	1PLL switching, Y2-to-Y3			80	110	ps
t_jit(cc)	Cycle-to-cycle jitter ⁽²⁾ ⁽³⁾	2PLL switching, Y2-to-Y5			130	200	ps
t_jit(per)	Peak-to-peak period jitter ⁽³⁾	1PLL switching, Y2-to-Y3			100	130	ps
t_jit(per)	Peak-to-peak period jitter ⁽³⁾	2PLL switching, Y2-to-Y5			150	220	ps
t_sk(o)	Output skew ⁽⁴⁾	f_OUT = 50MHz, Y1-to-Y3				50	ps
t_sk(o)	Output skew ⁽⁴⁾	f_OUT = 50MHz, Y2-to-Y5				110	ps
odc	Output duty cycle ⁽⁵⁾	f_VCO = 100MHz, Pdiv = 1		45%		55%
SDA AND SCL
V_IK	SCL and SDA input clamp voltage	V_DD = 1.7V, I_I = –18mA				–1.2	V
I_IH	SCL and SDA input current	V_I = V_DD, V_DD = 1.9V				±10	µA
V_IH	SDA/SCL input high voltage⁽⁶⁾			0.7 × V_DD			V
V_IL	SDA/SCL input low voltage⁽⁶⁾					0.3 × V_DD	V
V_OL	SDA low-level output voltage	I_OL = 3mA, V_DD = 1.7V				0.2 × V_DD	V
C_I	SCL/SDA Input capacitance	V_I = 0V or V_DD			3	10	pF

(1) All typical values are at respective nominal V_DD.

(2) 10,000 cycles

(3) Jitter depends on configuration. Jitter data is for input frequency = 27MHz, f_VCO = 135MHz, f_OUT = 27MHz. f_OUT = 3.072MHz or input frequency = 27MHz, f_VCO = 108MHz, f_OUT = 27MHz. f_OUT = 16.384MHz, f_OUT = 25MHz, f_OUT = 74.25MHz, f_OUT = 48MHz

(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider, data sampled on rising edge (t_r).

(5) odc depends on output rise- and fall-time (t_r/t_f);

(6) SDA and SCL pins are 3.3V tolerant.