SCAS946B November   2016  – March 2025 CDCLVP111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 LVECL DC Electrical Characteristics
    6. 5.6 LVPECL DC Electrical Characteristics
    7. 5.7 AC Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Fanout Buffer for Line Card Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 LVPECL Output Termination
          2. 7.2.1.2.2 Input Termination
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Supply Filtering
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 LVECL DC Electrical Characteristics

Vsupply: VCC = 0 V, VEE = –2.375 V to –3.8 V over operating temperature range TJ = –55°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
IEESupply internal currentAbsolute value of current–55°C, 25°C, 125°C3085mA
ICCOutput and internal supply currentAll outputs terminated 50Ω to VCC – 2V–55°C, 25°C385mA
125°C405
IINInput currentIncludes pullup and pulldown resistors,
VIH = VCC, VIL = VCC – 2V		–55°C, 25°C, 125°C–150150μA
VBBInternally generated bias voltageFor VEE = –3V to –3.8V, IBB = –0.2mA–55°C, 25°C, 125°C–1.45–1.3–1.125V
VEE = –2.375V to –2.75V, IBB = –0.2mA–55°C, 25°C, 125°C–1.3–1.25–1.1
VIHHigh-level input voltage (CLK_SEL)–55°C, 25°C, 125°C–1.165–0.88V
VILLow-level input voltage (CLK_SEL)–55°C, 25°C, 125°C–1.81–1.475V
VIDInput amplitude (CLKn, CLKn)Difference of input, see (1),
CDCLVP111-SP 		–55°C, 25°C, 125°C0.51.3V
VCMCommon-mode voltage (CLKn, CLKn)DC offset relative to VEE–55°C, 25°C, 125°CVEE + 1–0.3V
VOHHigh-level output voltageIOH = –21mA–55°C–1.26–0.85V
25°C–1.2–0.85
125°C–1.15–0.8
VOLLow-level output voltageIOL = –5mA25°C–1.85–1.425V
–55°C, 125°C–1.85–1.25
VODDifferential output voltage swingTerminated with 50Ω to VCC – 2V, see Figure 5-4–55°C, 25°C, 125°C350mV
(1) VID minimum and maximum is required to maintain AC specifications, actual device function tolerates a minimum VID of 100mV.