SCAS946B November   2016  – March 2025 CDCLVP111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 LVECL DC Electrical Characteristics
    6. 5.6 LVPECL DC Electrical Characteristics
    7. 5.7 AC Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Fanout Buffer for Line Card Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 LVPECL Output Termination
          2. 7.2.1.2.2 Input Termination
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Supply Filtering
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
7.2.1.2.2 Input Termination

The CDCLVP111-SP inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 7-4 illustrates how to DC couple an LVCMOS input to the CDCLVP111-SP. The series resistance (RS) must be placed close to the LVCMOS driver; the value is calculated as the difference between the transmission line impedance and the driver output impedance.

Refer to Figure 7-4 for proper input terminations, dependent on single ended or differential inputs.

CDCLVP111-SP DC-Coupled LVCMOS Input to CDCLVP111-SPFigure 7-4 DC-Coupled LVCMOS Input to CDCLVP111-SP

Figure 7-5 shows how to DC couple LVDS inputs to the CDCLVP111-SP. Figure 7-6 and Figure 7-7 describe the method of DC coupling LVPECL inputs to the CDCLVP111-SP for VCC = 2.5V and VCC = 3.3V, respectively.

CDCLVP111-SP DC-Coupled LVDS Inputs to CDCLVP111-SPFigure 7-5 DC-Coupled LVDS Inputs to CDCLVP111-SP
CDCLVP111-SP DC-Coupled LVPECL Inputs to CDCLVP111-SP (VCC = 2.5V)Figure 7-6 DC-Coupled LVPECL Inputs to CDCLVP111-SP (VCC = 2.5V)
CDCLVP111-SP DC-Coupled LVPECL Inputs to CDCLVP111-SP (VCC = 3.3V)Figure 7-7 DC-Coupled LVPECL Inputs to CDCLVP111-SP (VCC = 3.3V)

Figure 7-8 and Figure 7-9 show the technique of AC coupling differential inputs to the CDCLVP111-SP for VCC = 2.5V and VCC = 3.3V, respectively. TI recommends to place all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.

CDCLVP111-SP AC-Coupled Differential Inputs to CDCLVP111-SP (VCC = 2.5V)Figure 7-8 AC-Coupled Differential Inputs to CDCLVP111-SP (VCC = 2.5V)
CDCLVP111-SP AC-Coupled Differential Inputs to CDCLVP111-SP (VCC = 3.3V)Figure 7-9 AC-Coupled Differential Inputs to CDCLVP111-SP (VCC = 3.3V)