CDCLVP111-SP

ACTIVE

1:10 high speed clock buffer with selectable input clock driver

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1:10 high speed clock buffer with selectable input clock driver

CDCLVP111-SP

ACTIVE

Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 40 Output frequency (Max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 3.3 Core supply voltage (V) 3.3 Output skew (ps) 50 Features 1:10 fanout Operating temperature range (C) 25 to 25, -55 to 125 Rating Military, Space Output type LVPECL Input type CML, LVDS, LVPECL, SSTL open-in-new Find other Clock buffers

Package | Pins | Size

CFP (HFG) 36 82 mm² 9.078 x 9.078 open-in-new Find other Clock buffers

Features

  • Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
  • Fully Compatible With LVECL and LVPECL
  • Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typical 15 ps) for Clock-Distribution Applications
    • Additive Jitter Less Than 1 ps
    • Propagation Delay Less Than 355 ps
    • Open Input Default State
    • LVDS, CML, SSTL input Compatible
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Frequency Range From DC to 3.5 GHz
  • Supports Defense, Aerospace, and Medical Applications
    • Controlled Baseline
    • One Assembly and Test Site
    • One Fabrication Site
    • Available in Military (–55°C to 125°C) Temperature Range(1)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability
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Description

The CDCLVP111-SP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SP can accept two clock sources into an input multiplexer. The CDCLVP111-SP is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

For high-speed performance, the differential mode is strongly recommended.

The CDCLVP111-SP is characterized for operation from –55°C to 125°C.

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Technical documentation

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Type Title Date
* Data sheet CDCLVP111-SP Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver datasheet (Rev. A) Jan. 12, 2017
* SMD CDCLVP111-SP SMD 5962-16207 Sep. 22, 2020
* Radiation & reliability report CDCLVP111-SP Total Ionizing Dose (TID) Radiation Report (Rev. A) Jan. 07, 2020
* Radiation & reliability report Single-Event Effects Test Report for CDCLVP111-SP 1:10 LVPECL Clock Distributor Jan. 30, 2017
Selection guide TI Space Products (Rev. H) Jan. 27, 2021
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations May 18, 2020
Application note Single-Event Effects Confidence Interval Calculations Jan. 14, 2020
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing Jun. 17, 2019
E-book Radiation Handbook for Electronics (Rev. A) May 21, 2019
User guide TSW12D1620EVM-CVAL User's Guide (Rev. A) Jan. 29, 2019
User guide CDCLVP111-SP Evaluation Module (CDCLVP111EVM-CVAL) Nov. 17, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
999
Description
The CDCLVP111-SP EVM allows testing and validation of the CDCLVP111 clock distribution buffer utilizing a ceramic Engineering Model (EM).
Features
  • Distributes one of two differential input clocks to 10 differential LVPECL output clocks
  • Clock input selectable
  • Low output skew
  • Wide supply range

Design tools & simulation

SIMULATION MODEL Download
SLLM052B.ZIP (35 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
DESIGN TOOL Download
Clock tree architect programming software
CLOCK-TREE-ARCHITECT Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Features
  • Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
  • Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
  • Presents clear and intuitive block (...)

CAD/CAE symbols

Package Pins Download
CFP (HFG) 36 View options

Ordering & quality

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