SCAS946B November   2016  – March 2025 CDCLVP111-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 LVECL DC Electrical Characteristics
    6. 5.6 LVPECL DC Electrical Characteristics
    7. 5.7 AC Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Fanout Buffer for Line Card Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 LVPECL Output Termination
          2. 7.2.1.2.2 Input Termination
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Supply Filtering
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1.1 Design Requirements

The CDCLVP111-SP shown in Figure 7-1 is configured to be able to select 2 inputs, a 156.25MHz LVPECL clock from the backplane, or a secondary 156.25MHz LVCMOS 2.5V oscillator. Either signal can be then fanned out to desired devices, as shown.

The configuration example is driving 4 LVPECL receivers in a line card application with the following properties:

  • The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP111-SP needs to be provided with 86Ω emitter resistors near the driver for proper operation.
  • The ASIC is capable of DC coupling with a 2.5V LVPECL driver such as the CDCLVP111-SP. This ASIC features internal termination so no additional components are needed.
  • The FPGA requires external AC coupling but has internal termination. Again, 86Ω emitter resistors are placed near the CDCLVP111-SP and a 0.1µF are placed to provide AC coupling. Similarly, the CPU is internally terminated and requires external AC coupling capacitors.