SCDA060 May   2025 CD4053B

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Demultiplexing Application Example in Solar System
    2. 1.2 Application Issue of Unwanted Voltage at OFF Channels
  5. 2OFF Channel Model Analysis
    1. 2.1 Channel Structure
    2. 2.2 Equivalent Resistor Model
  6. 3Fix OFF Channel Output Voltage to Ground
    1. 3.1 Pull-down Resistor
    2. 3.2 Pull-down Capacitor
    3. 3.3 Bleeder Resistor With a Switch
  7. 4Test and Measurement
    1. 4.1 Measurement Considerations
    2. 4.2 Test Result
  8. 5Summary
  9. 6References

2.1 Channel Structure

Figure 2-3 shows the typical channel structure such as CD4053B. NMOS path are in parallel with PMOS path as in a transmission gate switch to achieve a flatter ON-state resistance. Two back-to-back NMOS transistors are utilized to compose the NMOS path, and another switch SW is connected between the mid-point of transistor pairs and VSS. When the channel is ON, transistors are ON, SW is OFF, and voltage signal is conveyed from input to output. When the channel is OFF, transistors are OFF, SW is ON, and the voltage of mid-point is pulled down to VSS.

Channel Structure of CD4053B Figure 2-3 Channel Structure of CD4053B

The PMOS path in Figure 2-3 works similarly to the NMOS path. Additionally, ESD diodes are placed at the IO pins to clamp the output voltage range to stay in between VDD and VSS in the case of an overvoltage event.

Assume the input is DC voltage, which is the example in Figure 1-5. Since both OFF-state transistors and ESD diode are not really OFF, there is a small amount of leakage current flowing through transistors and diodes to the output load. The OFF-channel leakage current paths are shown as in Figure 2-4.

OFF-channel Leakage Current Paths Figure 2-4 OFF-channel Leakage Current Paths

As mentioned above, when the channel is OFF, SW is ON and sinks the leakage current to VSS. Since the ON-state resistance of SW is much smaller than the OFF-state resistance of NMOS transistor, most of the leakage current from input side flows to VSS instead of output. Similarly, for the PMOS path, the leakage current loop forms between input and VDD, rather than between input and output. In other words, the channel structure in Figure 2-3 almost blocks input-to-output leakage paths (5)(6)(7)(8).

For the rest of output leakage paths (1)(2)(3)(4), current is sourced from VDD or is sunk by VSS. The sourcing and sinking current flows in opposite direction, canceling each other out to achieve a fairly low leakage current flowing through the output load.

Additionally, not all mux channel structure has the input-to-output leakage blocking feature. Take the channel structure in Figure 2-5 as an example:

Channel Structure Without Input-to-output Leakage Blocking Feature Figure 2-5 Channel Structure Without Input-to-output Leakage Blocking Feature

This structure does not have the additional switch path to guide the input leakage current to VDD/VSS. The OFF-channel leakage current paths are shown in Figure 2-6.

OFF-channel Leakage Current Paths With Input-to-to-output Leakage Figure 2-6 OFF-channel Leakage Current Paths With Input-to-to-output Leakage

The OFF-state resistance of NMOS provides paths (1)(2) for leakage current to flow from input to output. Other leakage current in paths (3)(4)(5)(6) cancel each other in opposite direction like in Figure 2-4. The leakage current in paths (1)(2) runs in the same direction and cannot cancel each other. Therefore, the output leakage of this structure can be larger.