SCES295AB June   2000  – October 2025 SN74LVC1G06

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics: –40°C to +85°C
    7. 5.7 Switching Characteristics: –40°C to +125°C
    8. 5.8 Operating Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 CMOS Open-Drain Outputs
      2. 6.3.2 Standard CMOS Inputs
      3. 6.3.3 Negative Clamping Diodes
      4. 6.3.4 Partial Power Down (Ioff)
      5. 6.3.5 Over-voltage Tolerant Inputs
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

6.3.2 Standard CMOS Inputs

The impendence for standard CMOS inputs is high. Typically, a CMOS input is modeled as a resistor in parallel with the input capacitance as shown in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in the Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal before the standard CMOS input.