SCES295AB June   2000  – October 2025 SN74LVC1G06

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics: –40°C to +85°C
    7. 5.7 Switching Characteristics: –40°C to +125°C
    8. 5.8 Operating Characteristics
    9. 5.9 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 CMOS Open-Drain Outputs
      2. 6.3.2 Standard CMOS Inputs
      3. 6.3.3 Negative Clamping Diodes
      4. 6.3.4 Partial Power Down (Ioff)
      5. 6.3.5 Over-voltage Tolerant Inputs
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

3 Description

This single inverter buffer and driver is designed for 1.65V to 5.5V VCC operation.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The output of the SN74LVC1G06 device is open-drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32mA.

This device is fully specified for partial-power-down applications using Ioff.The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM)(3)
SN74LVC1G06 DBV (SOT-23, 5) 2.90mm × 2.80mm 2.90mm × 1.60mm
DCK (SC70, 5) 2.00mm × 2.10mm 2.00mm × 1.25mm
DRL (SOT-5X3, 5) 1.60mm × 1.60mm 1.60mm × 1.20mm
DRY (USON, 6) 1.45mm × 1.00mm 1.45mm × 1.00mm
DSF (X2SON, 6) 1.00mm × 1.00mm 1.00mm × 1.00mm
YZP (DSBGA, 5) 1.75mm × 1.25mm 1.40mm × 0.90mm
YZV (DSBGA, 4) 1.25mm × 1.25mm 0.90mm × 0.90mm
DPW (X2SON, 5) 0.80mm × 0.80mm 0.80mm × 0.80mm
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN74LVC1G06 Logic Diagram (Positive Logic) Logic Diagram (Positive Logic)