SCES558E July   2004  – January 2025 SN74LVC2G14-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics, –40°C to 85°C
    7. 4.7 Switching Characteristics, –40°C to 125°C
    8. 4.8 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 CMOS Schmitt-Trigger Inputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Typical Application
        1. 7.1.1.1 Design Requirements
          1. 7.1.1.1.1 Power Considerations
          2. 7.1.1.1.2 Input Considerations
          3. 7.1.1.1.3 Output Considerations
        2. 7.1.1.2 Detailed Design Procedure
        3. 7.1.1.3 Application Curve
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage Operating 1.65 5.5 V
Data retention only 1.5
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
IOH High-level output current VCC = 1.65 V –4 mA
VCC = 2.3 V –8
VCC = 3 V –16
–24
VCC = 4.5 V –32
IOL Low-level output current VCC = 1.65 V 4 mA
VCC = 2.3 V 8
VCC = 3 V 16
24
VCC = 4.5 V 32
TA Operating free-air temperature –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.