SCES582I July   2004  – February 2025 SN74AVCH2T45

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics: VCCA = 1.2V
    7. 5.7  Switching Characteristics: VCCA = 1.5V
    8. 5.8  Switching Characteristics: VCCA = 1.8V
    9. 5.9  Switching Characteristics: VCCA = 2.5V
    10. 5.10 Switching Characteristics: VCCA = 3.3V
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Characteristics
      1. 5.12.1 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 1.8V
      2. 5.12.2 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 2.5V
      3. 5.12.3 Typical Propagation Delay (A to B) vs Load Capacitance, TA = 25°C, VCCA = 3.3V
  7. 6 Parameter Measurement Information
    1. 6.1 23
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VCC Isolation
      2. 7.3.2 2-Rail Design
      3. 7.3.3 IO Ports are 4.6 V Tolerant
      4. 7.3.4 Partial Power Down Mode
      5. 7.3.5 Bus Hold on Data Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Unidirectional Logic Level-Shifting Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bidirectional Logic Level-Shifting Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Enable Times
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.2.2 Detailed Design Procedure

Table 8-2 lists a sequence that shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.

Table 8-2 Data Transmission Sequence
STATEDIR CTRLIO-1IO-2DESCRIPTION
1HOutputInputSYSTEM-1 data to SYSTEM-2
2HHi-ZHi-ZSYSTEM-2 is getting ready to send data to SYSTEM-1. IO-1 and IO-2 are disabled.
The bus-line state depends on pull-up or pull-down.(1)
3LHi-ZHi-ZDIR bit is flipped. IO-1 and IO-2 still are disabled.
The bus-line state depends on pull-up or pull-down.(1)
4LInputOutputSYSTEM-2 data to SYSTEM-1
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.