SCES791B August   2009  – August 2025 TXB0106-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
    1.     Pin Functions
  6. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics (TXB0106I)
    6. 5.6  Electrical Characteristics (TXB0106)
    7. 5.7  Timing Requirements – VCCA = 1.2V, TA = 25°C
    8. 5.8  Timing Requirements – VCCA = 1.5V ± 0.1V
    9. 5.9  Timing Requirements – VCCA = 1.8V ± 0.15V
    10. 5.10 Timing Requirements – VCCA = 2.5V ± 0.2V
    11. 5.11 Timing Requirements – VCCA = 3.3V ± 0.3V
    12. 5.12 Switching Characteristics –VCCA = 1.2V, TA = 25°C
    13. 5.13 Switching Characteristics – VCCA = 1.5V ± 0.1V (TXB0106I)
    14. 5.14 Switching Characteristics – VCCA = 1.5V ± 0.1V (TXB0106)
    15. 5.15 Switching Characteristics – VCCA = 1.8V ± 0.15V (TXB0106I)
    16. 5.16 Switching Characteristics – VCCA = 1.8V ± 0.15V (TXB0106)
    17. 5.17 Switching Characteristics – VCCA = 2.5V ± 0.2V (TXB0106I)
    18. 5.18 Switching Characteristics – VCCA = 2.5V ± 0.2V (TXB0106)
    19. 5.19 Switching Characteristics – VCCA = 3.3V ± 0.3V (TXB0106I)
    20. 5.20 Switching Characteristics – VCCA = 3.3V ± 0.3V (TXB0106)
    21. 5.21 Operating Characteristics
    22. 5.22 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Architecture
      2. 6.3.2 Input Driver Requirements
      3. 6.3.3 Power Up
      4. 6.3.4 Output Load Considerations
      5. 6.3.5 Enable and Disable
      6. 6.3.6 Pullup or Pulldown Resistors on I/O Lines
    4. 6.4 Device Functional Modes
  8.   Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Third-Party Products Disclaimer
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

6.3.4 Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading and to ensure that proper one-shot (O.S.) triggering takes place. PCB signal trace-lengths should be kept short enough such that the round trip delay of any reflection is less than the O.S. duration. This improves signal integrity by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay on for approximately 10ns. The maximum capacitance of the lumped load that can be driven also depends directly on the O.S. duration. With very heavy capacitive loads, the O.S. can time out before the signal is driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC, load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the capacitance that the TXB0106-Q1 output sees, so it is recommended that this lumped-load capacitance be considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level affects.