SCES874A March   2017  – August 2026 SN74LVC1G79-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: TA = –40°C to +85°C
    7. 5.7  Timing Requirements: TA = –40°C to +125°C
    8. 5.8  Switching Characteristics: CL = 15pF, TA = –40°C to +85°C
    9. 5.9  Switching Characteristics: CL = 30 or 50pF, TA = –40°C to +85°C
    10. 5.10 Switching Characteristics: CL = 30pF or 50pF, TA = –40°C to +125°C
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 6.3.2 Standard CMOS Inputs
      3. 6.3.3 Clamp Diodes
      4. 6.3.4 Partial Power Down (Ioff)
      5. 6.3.5 Over-Voltage Tolerant Inputs
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

3 Description

The SN74LVC1G79-Q1 device is an automotive AEC-Q100 qualified single positive-edge-triggered D-type flip-flop that is designed for 1.65V to 5.5V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Packaging Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
SN74LVC1G79QDCKRQ1SC70 (5)2.00mm × 1.25mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
SN74LVC1G79-Q1 Logic Diagram (Positive Logic) Logic Diagram (Positive Logic)