SCET013 june 2023 SN74LVC1G14 , SN74LVC1G14-Q1 , SN74LVC1G17 , SN74LVC1G17-Q1 , SN74LVC2G14 , SN74LVC2G14-Q1
On device start-up, some logic parts may output an invalid state until cleared. A pulse can be generated when VCC turns on to reset those parts to valid output states.
Design Considerations
- The pulse width is determined by
T = RC
- The standard configuration for a 1-ms pulse is R = 10 kΩ, C = 0.1 µF
- Multiple reset pulse generators with different RCs can be used to delay the pulse to some devices, resetting some before others or triggering clock inputs
- [FAQ] How does a slow or floating input affect a CMOS device?
- [FAQ] Where do I find maximum power dissipation for a device?
- Ask a question on the TI E2E™ forum
Recommended Parts
| Part Number | AEC-Q100 | VCC Range | Channels | Features |
|---|---|---|---|---|
| SN74LVC1G14 | 1.65 V – 5.5 V | Inverting buffer | 1 channel, Schmitt-trigger inputs | |
| SN74LVC1G14-Q1 | ✓ | |||
| SN74LVC2G14 | 1.65 V – 5.5 V | Inverting buffer | 2 channel, Schmitt-trigger inputs | |
| SN74LVC2G14-Q1 | ✓ | |||
| SN74LVC1G17 | 1.65 V – 5.5 V | Buffer | 1 channel, Schmitt-trigger inputs | |
| SN74LVC1G17-Q1 | ✓ |
For more devices, browse through the online parametric tool where you can sort by desired voltage, channel numbers, and other features.