SN74LVC2G14

DSBGA (YZP)

6

2 mm² .928 x 1.428

SOT-23 (DBV)

6

5 mm² 2.9 x 1.6

SOT-SC70 (DCK)

6

4 mm² 2 x 2.1

Available in the TI NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 5.4 ns at 3.3 V
Low-Power Consumption, 10-μA Maximum I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Support Translation Down
(5 V to 3.3 V; 3.3 V to 1.8 V)
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II

Available in the TI NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 5.4 ns at 3.3 V
Low-Power Consumption, 10-μA Maximum I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Support Translation Down
(5 V to 3.3 V; 3.3 V to 1.8 V)
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II

This dual Schmitt-trigger inverter is designed for
1.65-V to 5.5-V V_CC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC2G14 device contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (V_T+) and negative-going (V_T–) signals.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For all available packages, see the orderable addendum at the end of the data sheet.

This dual Schmitt-trigger inverter is designed for
1.65-V to 5.5-V V_CC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC2G14 device contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (V_T+) and negative-going (V_T–) signals.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For all available packages, see the orderable addendum at the end of the data sheet.

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Technical documentation

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	Type	Title	Date
*	Data sheet	SN74LVC2G14 Dual Schmitt-Trigger Inverter datasheet (Rev. O)	10 Aug 2015
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 Jul 2021
	Application note	Converting SPI to GPIO Through Digital Isolators	16 Oct 2020
	Selection guide	Little Logic Guide 2018 (Rev. G)	06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)	26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dec 2015
	Application note	Understanding Schmitt Triggers	21 Sep 2011
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	More literature	Design Summary for WCSP Little Logic (Rev. B)	04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	User guide	Signal Switch Data Book (Rev. A)	14 Nov 2003
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits	06 Nov 2003
	More literature	Logic Cross-Reference (Rev. A)	07 Oct 2003
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)	18 Dec 2002
	Application note	Texas Instruments Little Logic Application Report	01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 May 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 May 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	27 Mar 2002
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	01 Dec 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	01 Jun 1997
	Application note	LVC Characterization Information	01 Dec 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 Oct 1996
	Application note	Live Insertion	01 Oct 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide	01 Sep 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

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Simulation model

SN74LVC2G14 IBIS Model (Rev. B)

SCEM252B.ZIP (45 KB) - IBIS Model

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Simulation model

SN74LVC2G14 Behavioral SPICE Model

SCEM616.ZIP (7 KB) - PSpice Model

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