SCEU029B August   2024  – June 2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Functional Blocks
      1. 2.1.1 Test Points
      2. 2.1.2 Programmer Header Block (P1)
      3. 2.1.3 External Connection Header Block
      4. 2.1.4 GPI Protection Block
      5. 2.1.5 I2C Address Block
      6. 2.1.6 Interface Select Block
      7. 2.1.7 RWS/RWB Socket
    2. 2.2 GPIO Testing Blocks
      1. 2.2.1 LED Blocks
      2. 2.2.2 Switch/LED Blocks
      3. 2.2.3 Switch Block
      4. 2.2.4 LED/Potentiometer Blocks
  9. 3Software
    1. 3.1 Using the TPLD1202-RWS-EVM
      1. 3.1.1 Equipment Needed for Programming
      2. 3.1.2 Installing Software
    2. 3.2 Configuring a TPLD Device
      1. 3.2.1 TPLD1202-RWS-EVM Setup for Programming
      2. 3.2.2 Inserting a TPLD1202RWS into the RWS/RWB Socket
      3. 3.2.3 Connecting the TPLD1202-RWS-EVM to a TPLD-PROGRAM Board
      4. 3.2.4 Temporarily Configuring a TPLD Device
      5. 3.2.5 Permanently Programming a TPLD Device
    3. 3.3 Using the TPLD1202-RWS-EVM to Program TPLD1202RWB or TPLD1202RWS
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
      1. 4.2.1 PCB Overview
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6References
  13. 7Revision History

2.1.3 External Connection Header Block

Use the P2 header block to interface the TPLD1202-RWS-EVM with an external system. Using the guide printed on the EVM silkscreen, interface the TPLD pins with an external system to allow for prototyping and testing in customer systems. When supplying power to the TPLD using the P2 header block, SW4 must be in the OFF position and a shunt placed on J1, connecting the external VCC supply from P2 (VCC_EXT) to the VCC net of the EVM. TI recommends not connecting the board to an external system and to the TPLD-PROGRAM at the same time to avoid the risk of damage to the TPLD-PROGRAM and the external system.

TPLD1202-RWS-EVM P2 and J1 Headers Figure 2-1 P2 and J1 Headers