Due to the FET based architecture of this translator, there are some considerations a system designer must be aware of during powering up with large differences in capacitance between the sides. If one supply with smaller capacitance is already powered up, and the other is ramping (with OE pin high), the side with the heavier load can ramp slower than the power supply ramp, due to only having an internal 10kΩ pull up resistor. In this situation, once the rising POR threshold is met, the device enables all circuitry. If the heavy capacitance side has not yet risen above about 70% of supply, the device determines this as low, and briefly turns on the fall time accelerators to propagate a low. Once the fall time accelerator has timed out, the signals rise and sit idle high.

This phenomenon can be eliminated by holding the OE pin low (disabled) until all supplies and busses have ramped up, since this explicitly disables the bus acceleration circuitry until the bus has completed power up. Slower supply ramps also help reduce this since the bus voltage follows the supply closer if the ramp is slow.