SCPS292 July   2025 TCA9539A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 RESET Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 RESET Input
      3. 7.3.3 Interrupt ( INT) Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
    6. 7.6 Register Map
      1. 7.6.1 Device Address
      2. 7.6.2 Control Register And Command Byte
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating Junction Temperature and Power Dissipation
        2. 8.2.2.2 Minimizing ICC When I/Os Control LEDs
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 PW Package, 24-Pin TSSOP (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 INT O Interrupt open-drain output. Connect to VCC through a pull-up resistor
2 A1 I Address input. Connect directly to VCC or ground
3 RESET I Active-low reset input. Connect to VCC through a pull-up resistor if no active connection is used
4 P00 I/O P-port input-output. Push-pull design structure. At power-on, P00 is configured as an input
5 P01 I/O P-port input-output. Push-pull design structure. At power-on, P01 is configured as an input
6 P02 I/O P-port input-output. Push-pull design structure. At power-on, P02 is configured as an input
7 P03 I/O P-port input-output. Push-pull design structure. At power-on, P03 is configured as an input
8 P04 I/O P-port input-output. Push-pull design structure. At power-on, P04 is configured as an input
9 P05 I/O P-port input-output. Push-pull design structure. At power-on, P05 is configured as an input
10 P06 I/O P-port input-output. Push-pull design structure. At power-on, P06 is configured as an input
11 P07 I/O P-port input-output. Push-pull design structure. At power-on, P07 is configured as an input
12 GND — Ground
13 P10 I/O P-port input-output. Push-pull design structure. At power-on, P10 is configured as an input
14 P11 I/O P-port input-output. Push-pull design structure. At power-on, P11 is configured as an input
15 P12 I/O P-port input-output. Push-pull design structure. At power-on, P12 is configured as an input
16 P13 I/O P-port input-output. Push-pull design structure. At power-on, P13 is configured as an input
17 P14 I/O P-port input-output. Push-pull design structure. At power-on, P14 is configured as an input
18 P15 I/O P-port input-output. Push-pull design structure. At power-on, P15 is configured as an input
19 P16 I/O P-port input-output. Push-pull design structure. At power-on, P16 is configured as an input
20 P17 I/O P-port input-output. Push-pull design structure. At power-on, P17 is configured as an input
21 A0 I Address input. Connect directly to VCC or ground
22 SCL I Serial clock bus. Connect to VCC through a pull-up resistor
23 SDA I/O Serial data bus. Connect to VCC through a pull-up resistor
24 VCC — Supply voltage