SDAA058 September   2025 TDP0604

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Test Setup
    1. 2.1 Block Diagram
    2. 2.2 Aardvark I2C and SPI Controller
    3. 2.3 EDID Emulator
    4. 2.4 Enable TDP0604 in I2C Mode and Set Target I2C Address
  6. 3TDP0604 Controls for HDMI Compliance Testing
    1. 3.1 Data Eye Diagram in Different EQ
      1. 3.1.1 HDMI2.0 Test with Resolution 4096 × 2160_60p_8bit_444
        1. 3.1.1.1 D1 NegativeLane, EQ = 0
        2. 3.1.1.2 D1 NegativeLane, EQ = 4
        3. 3.1.1.3 D1 NegativeLane, EQ = F
      2. 3.1.2 HDMI1.4 Test with Resolution 4096 × 2160_30p_8bit_444
        1. 3.1.2.1 Source Eye Diagram: CK - D1, EQ = 0
        2. 3.1.2.2 Source Eye Diagram: CK - D1, EQ = 4
        3. 3.1.2.3 Source Eye Diagram: CK - D1, EQ = F
      3. 3.1.3 HDMI1.4 Test with Resolution 720 × 480_60p_8bit_444
        1. 3.1.3.1 Source Eye Diagram: CK - D1, EQ=0
        2. 3.1.3.2 Source Eye Diagram: CK - D1, EQ = 4
        3. 3.1.3.3 Source Eye Diagram: CK - D1, EQ = F
    2. 3.2 Rising and Falling Resulting in Different Slew Rates
      1. 3.2.1 HDMI2.0 Test with Resolution 4096 × 2160_60p_8bit_444
        1. 3.2.1.1 TRISE, TFALL when SLEW_3G =3h, SLEW_6G=0h, SLEW_CLK 0 =0h
        2. 3.2.1.2 TRISE, TFALL when SLEW_3G =3h, SLEW_6G=1h, SLEW_CLK 0 =1h
        3. 3.2.1.3 TRISE, TFALL when SLEW_3G =3h, SLEW_6G=7h, SLEW_CLK 0 =7h
      2. 3.2.2 HDMI1.4 Test with Resolution 4096 × 2160_30p_8bit_444
      3. 3.2.3 TRISE, TFALL when SLEW_3G =0h, SLEW_6G=1h, SLEW_CLK 0 =0h
      4. 3.2.4 TRISE, TFALL when SLEW_3G =3h, SLEW_6G=1h, SLEW_CLK 0 =1h
      5. 3.2.5 TRISE, TFALL when SLEW_3G =7h, SLEW_6G=1h, SLEW_CLK 0 =7h
      6. 3.2.6 HDMI1.4 Test with Resolution 720 × 480_60p_8bit_444
        1. 3.2.6.1 TRISE, TFALL when SLEW_3G = 0h, SLEW_6G = 1h, SLEW_CLK 0 = 0h
        2. 3.2.6.2 TRISE, TFALL when SLEW_3G = 3h, SLEW_6G = 1h, SLEW_CLK 0 = 1h
        3. 3.2.6.3 TRISE, TFALL when SLEW_3G = 7h, SLEW_6G = 1h, SLEW_CLK 0 = 7h
    3. 3.3 VL and VSwing
      1. 3.3.1 HDMI2.0 Test with Resolution 4096 × 2160_60p_8bit_444
        1. 3.3.1.1 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h
        2. 3.3.1.2 VL and VSwing with HDMI20_VOD =1h (default 1000mV), HDMI14_VOD =1h (default 1000mV)
        3. 3.3.1.3 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h
      2. 3.3.2 HDMI1.4 Test with Resolution 4096 x 2160_30p_8bit_444
        1. 3.3.2.1 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD = 0h, Use Values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD = 0h, Limited -15%
        2. 3.3.2.2 VL and VSwing with HDMI20_VOD =1h (Default 1000mV), HDMI14_VOD =1h (Default 1000mV)
        3. 3.3.2.3 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h, Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD = 7h, Limited +20%)
      3. 3.3.3 HDMI1.4 Test with Resolution 720 x 480_60p_8bit_444
        1. 3.3.3.1 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h,Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD = 0h, Limited -15%)
        2. 3.3.3.2 VL and VSwing with HDMI20_VOD =1h (default 1000mV), HDMI14_VOD =1h (default 1000mV)
        3. 3.3.3.3 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h, use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD = 7h, Limited +20%)
    4. 3.4 HDMI1.4-2.0 Pass Compliance Test Pass Result
      1. 3.4.1 HDMI2.0 Test with Resolution 4096x2160_60p_8bit_444
      2. 3.4.2 HDMI1.4 Test With Resolution 4096 × 2160_30p_8bit_444
      3. 3.4.3 HDMI1.4 Test with Resolution 720 x 480_60p_8bit_444
  7. 4Tips
  8. 5Summary
  9. 6References

2.1 Block Diagram

The DUT is a motherboard (MB) with TDP0604 and the Aardvark I2C/SPI controller is used as the I2C host to config TDP0604, the MB HDMI port connects to a test fixture. The fixture breaks out the HDMI three TMDS data lane, one clock lane, and the DDC bus. The three TMDS data and the clock lane are connected to an oscilloscope for the electrical compliance testing. The DDC bus is connected to an EDID emulator that acts as a HDMI sink to let the MB detecting as a monitor and send the display signal out.

Block Diagram of the Test PlatformFigure 2-1 Block Diagram of the Test Platform