SDAA058 September   2025 TDP0604

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Test Setup
    1. 2.1 Block Diagram
    2. 2.2 Aardvark I2C and SPI Controller
    3. 2.3 EDID Emulator
    4. 2.4 Enable TDP0604 in I2C Mode and Set Target I2C Address
  6. 3TDP0604 Controls for HDMI Compliance Testing
    1. 3.1 Data Eye Diagram in Different EQ
      1. 3.1.1 HDMI2.0 Test with Resolution 4096 × 2160_60p_8bit_444
        1. 3.1.1.1 D1 NegativeLane, EQ = 0
        2. 3.1.1.2 D1 NegativeLane, EQ = 4
        3. 3.1.1.3 D1 NegativeLane, EQ = F
      2. 3.1.2 HDMI1.4 Test with Resolution 4096 × 2160_30p_8bit_444
        1. 3.1.2.1 Source Eye Diagram: CK - D1, EQ = 0
        2. 3.1.2.2 Source Eye Diagram: CK - D1, EQ = 4
        3. 3.1.2.3 Source Eye Diagram: CK - D1, EQ = F
      3. 3.1.3 HDMI1.4 Test with Resolution 720 × 480_60p_8bit_444
        1. 3.1.3.1 Source Eye Diagram: CK - D1, EQ=0
        2. 3.1.3.2 Source Eye Diagram: CK - D1, EQ = 4
        3. 3.1.3.3 Source Eye Diagram: CK - D1, EQ = F
    2. 3.2 Rising and Falling Resulting in Different Slew Rates
      1. 3.2.1 HDMI2.0 Test with Resolution 4096 × 2160_60p_8bit_444
        1. 3.2.1.1 TRISE, TFALL when SLEW_3G =3h, SLEW_6G=0h, SLEW_CLK 0 =0h
        2. 3.2.1.2 TRISE, TFALL when SLEW_3G =3h, SLEW_6G=1h, SLEW_CLK 0 =1h
        3. 3.2.1.3 TRISE, TFALL when SLEW_3G =3h, SLEW_6G=7h, SLEW_CLK 0 =7h
      2. 3.2.2 HDMI1.4 Test with Resolution 4096 × 2160_30p_8bit_444
      3. 3.2.3 TRISE, TFALL when SLEW_3G =0h, SLEW_6G=1h, SLEW_CLK 0 =0h
      4. 3.2.4 TRISE, TFALL when SLEW_3G =3h, SLEW_6G=1h, SLEW_CLK 0 =1h
      5. 3.2.5 TRISE, TFALL when SLEW_3G =7h, SLEW_6G=1h, SLEW_CLK 0 =7h
      6. 3.2.6 HDMI1.4 Test with Resolution 720 × 480_60p_8bit_444
        1. 3.2.6.1 TRISE, TFALL when SLEW_3G = 0h, SLEW_6G = 1h, SLEW_CLK 0 = 0h
        2. 3.2.6.2 TRISE, TFALL when SLEW_3G = 3h, SLEW_6G = 1h, SLEW_CLK 0 = 1h
        3. 3.2.6.3 TRISE, TFALL when SLEW_3G = 7h, SLEW_6G = 1h, SLEW_CLK 0 = 7h
    3. 3.3 VL and VSwing
      1. 3.3.1 HDMI2.0 Test with Resolution 4096 × 2160_60p_8bit_444
        1. 3.3.1.1 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h
        2. 3.3.1.2 VL and VSwing with HDMI20_VOD =1h (default 1000mV), HDMI14_VOD =1h (default 1000mV)
        3. 3.3.1.3 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h
      2. 3.3.2 HDMI1.4 Test with Resolution 4096 x 2160_30p_8bit_444
        1. 3.3.2.1 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD = 0h, Use Values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD = 0h, Limited -15%
        2. 3.3.2.2 VL and VSwing with HDMI20_VOD =1h (Default 1000mV), HDMI14_VOD =1h (Default 1000mV)
        3. 3.3.2.3 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h, Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD = 7h, Limited +20%)
      3. 3.3.3 HDMI1.4 Test with Resolution 720 x 480_60p_8bit_444
        1. 3.3.3.1 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h,Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD = 0h, Limited -15%)
        2. 3.3.3.2 VL and VSwing with HDMI20_VOD =1h (default 1000mV), HDMI14_VOD =1h (default 1000mV)
        3. 3.3.3.3 VL and VSwing with HDMI20_VOD =0h, HDMI14_VOD =0h, use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD = 7h, Limited +20%)
    4. 3.4 HDMI1.4-2.0 Pass Compliance Test Pass Result
      1. 3.4.1 HDMI2.0 Test with Resolution 4096x2160_60p_8bit_444
      2. 3.4.2 HDMI1.4 Test With Resolution 4096 × 2160_30p_8bit_444
      3. 3.4.3 HDMI1.4 Test with Resolution 720 x 480_60p_8bit_444
  7. 4Tips
  8. 5Summary
  9. 6References

4 Tips

TDP0604 reads the last value snooped through DDC read/write or I2C write. Use I2C host to read the TMDS_CLK_RATIO [1] bit in SCDC_TMDS_CONFIG Register (Offset = 20h) to find the correct TMDS clock period ratio.

Table 4-1 TMDS_CLK_Ratio Bit
BitFieldTypeResetDescription
7-2RESERVEDR0hReserved
1TMDS_CLK_RATIORH/W0hTMDS Bit Period to TMDS Clock Period Ratio. Reads last value snooped through DC read/write or I2C write
0RESERVEDR0hReserved

When reading is HDMI2.0 clock ratio:

TMDS_CLK_RATIO = 1 Figure 4-1 TMDS_CLK_RATIO = 1

When reading back is HDMI1.4 clock ratio:

TMDS_CLK_RATIO = 0 Figure 4-2 TMDS_CLK_RATIO = 0