SDAA233 December   2025 TPS7H4102-SEP , TPS7H4104-SEP , TPS7H4104-SP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Concept of Operation
  6. 3Maintaining Output Accuracy
  7. 4Simulation Results
    1. 4.1 VEXT Output Deviation Effects
  8. 5Test Results With TPS7H4104EVM
  9. 6Summary
  10. 7References

4 Simulation Results

A simulation was configured and run using the TPS7H4104-SEP SIMPLIS model provided on ti.com. CH2 was used as VEXT and CH3 as VOUT. Channels 1 and 4 are unused in the simulation and are therefore disabled and not shown in Figure 4-1. CH2 was not modified from the original configuration and is set to output 1.2V. CH3 was modified to output a voltage below VREF, in this case 0.5V was selected. 10.02kΩ was selected for the top resistance of the VOUT (CH3) feedback divider to match the default values on the TPS7H4104EVM. Equation 3 calculates the bottom resistor value.

Equation 3. RB1=RT1VEXT-VREFVREF-VOUT

Using the following inputs results in RB1 = 61.24kΩ:

  • RT1 = 10.02kΩ
  • VEXT = 1.207V
  • VREF = 0.59948V
  • VOUT = 0.5V

61.9kΩ was selected for the resistor in the simulation as the closest E96 series value to the calculation result. A switching frequency of approximately 300kHz was also configured for this simulation to avoid violating the minimum on-time specification of the device in the data sheet. RT, COMP and RSC for CH3 were also configured using the equations found in the TPS7H4104 data sheet.

Simulation SchematicFigure 4-1 Simulation Schematic

Startup was simulated with the internal channel sequencing enabled. Since the internal sequencer of the TPS7H4104 brings up channels in numbered order, and CH2 was used for VREF while CH3 was used for VOUT, the sequencer enables VOUT only after VEXT has finished the soft startup sequence. The plot below shows VOUT and VEXT during startup and steady-state operation with a load of 3A applied to VOUT. As expected, VOUT regulates to 0.5V, which is 100mV below VREF as shown in Figure 4-2.

Simulation Startup ResultsFigure 4-2 Simulation Startup Results

Using a simulation allows the ability to vary the internal voltage reference between simulation runs. VREF was set to the Min, Typ, and Max values shown in the TPS7H4104 data sheet, and the RMS value of VOUT from 6ms to 10ms of the simulation was recorded. The RMS values for VOUT along with the corresponding VREF values are shown in Table 4-1. The percentage shift from the typical value is also calculated for VREF and for VOUT.

Table 4-1 VREF To VOUT Error Propagation
ValueVREF (mV)VREF Change (%)VOUT (mV)VOUT Change (%)
Typ599.48-501.04-
Min591.50-1.33%494.38-1.33%
Max603.500.67%504.400.67%

Table 4-1 shows that VREF changes are propagated to VOUT without adding extra error. So, a 1% change in VREF results in a 1% change in VOUT. This behavior is consistent with the equation for VOUT that was shown in Section 3, as there is only a single VREF term to contribute error to VOUT. This is the same error propagation from VREF that is seen in a single-channel setup regulating at or above VREF, so the goal of creating a channel that regulates below VREF while maintaining the same accuracy has been achieved.