1 Introduction to Mixed-Voltage Logic in TPLD

The demand for smaller, more power-efficient devices is driving many semiconductor devices and circuit designs to use lower supply voltage levels, such as 1.8V. These advances in technology and manufacturing are challenged by managing integration with existing devices or complying with industry standards that potentially require higher supply voltages, such as 3.3V or 5V. To address these challenges, voltage level translation is a feature in logic devices which serves as a bridge between devices like processors, sensors, and devices of different generations. See Basics of Voltage-Level Translation for a comprehensive explanation of voltage translation.

TI programmable logic devices (TPLDs) can up-translate and down-translate voltages, allowing for the use of several different logic levels. All TPLDs have an optional low-voltage digital input mode for the input pins, allowing for 1.8V logic inputs across all supply voltages. Similarly, the TPLD can facilitate voltage translation with an optional open-drain NMOS output mode. Details about how to use these TPLD features can be found at Up and Down Translation in TI's Programmable Logic Devices (TPLD).