SDAA373 August   2026 LM51770

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Automotive LED Application Requirements and System Overview
    1. 2.1 Application Requirements
    2. 2.2 Typical Automotive Headlight System Overview
    3. 2.3 LED Load Configuration and Switching Architecture
  6. 3LM51770-Q1 Pin Configuration for ILIM Function
    1. 3.1 LM51770-Q1 Pin Description
    2. 3.2 Pin Configuration for ILIM Operation
  7. 4Automotive LED Lighting Design Application
    1. 4.1 Power Stage Design
    2. 4.2 Control Loop Architecture
  8. 5ILIM Loop Optimization and Measurement Results
    1. 5.1 Strong Voltage Loop Compensation
    2. 5.2 Weak Voltage Loop Compensation
    3. 5.3 LED Switching and Buck-Boost Region
  9. 6Detailed Results
    1. 6.1 LED Steady State Operation Results
    2. 6.2 LED Switching State Operation Results
  10. 7Summary
  11. 8References

3.2 Pin Configuration for ILIM Operation

The constant output current regulation of the LED driver is implemented via the integrated average current limiter of the LM51770-Q1. The pins of CFG, SYNC, ISNSP/ISNSN, and IMONOUT are associated with this function. Proper configuration of these pins ensures accurate constant current output, stable loop operation, and suppressed current overshoot during LED load switching. Figure 3-1 shows these pins in the application.

Pin Configuration for CC Operation Figure 3-1 Pin Configuration for CC Operation

1. CFG

The LM51770-Q1's CFG pin is programmed with a single precision resistor that is sampled and latched during the device’s power‑up sequence; the resistor value selects the operating mode (DRSS behavior, SCP‑Hiccup activation, PSM entry threshold, and current‑limit setting) as defined in Section 8.3.16 of the LM51770-Q1 datasheet. For the headlamp application we use Setting #5 (RCFG=22.7kΩ), which activates the average‑current regulation loop and thereby provides a stable constant‑current drive for the high‑beam, low‑beam, and corner‑light LED modules.

2. SYNC

The SYNC pin determines the direction of the LM51770-Q1's current‑limit function; its state is sampled and latched at power‑up. For this unidirectional LED‑driver application the SYNC pin must be pulled high during startup, which configures the current‑limit circuitry to operate in the forward‑direction required for the high‑beam, low‑beam, and corner‑light LED strings.

3. ISNSP/ISNSN

The ISNSP and ISNSN pins form the differential input of the LM51770-Q1's internal average current sense amplifier; they set the target output current by sensing the voltage across an external sense resistor (RISNS) placed in series with the LED load on the output side. The differential voltage generated by RISNS is applied to ISNSP/ISNSN, and the resistor value directly determines the regulated constant‑current magnitude—selecting RISNS according to the desired LED current establishes the driver’s set‑point. The value of RISNS is calculated by:

Equation 1. R I S N S = Δ V ( I S N S ) I O U T ( C C )

Where, ΔV(ISNS) is current sense offset and threshold voltage, 50mV in datasheet, IOUT(CC) is the target constant output current, set to 1A in this design

4. IMONOUT

The IMONOUT pin is the compensation node for the LM51770-Q1's average‑current loop and can also output an analog current monitor signal. In constant‑current mode connect a series RC network (RCOMP and CCOMP) from IMONOUT to AGND; the resistor sets the loop bandwidth and the capacitor provides the necessary phase‑lead to achieve adequate phase margin, ensuring stability and minimizing overshoot/undershoot across the full input‑voltage and load range. Detailed component values are given in the loop‑compensation section.

Other Important Pin Configurations:

5. FB

The FB pin programs the maximum output voltage through an external resistor divider, set to 55V for this headlight application. During constant-current LED operation, the voltage loop provides secondary overvoltage protection by clamping the output voltage at 55V if the LED load opens, preventing converter and downstream circuit damage. The voltage loop also facilitates seamless transitions between current and voltage regulation modes during load variations.

The maximum output voltage VOUT(max) is established by a resistive divider network consisting of RFBT (connected between VOUT and FB) and RFBB (connected between FB and AGND). The converter regulates the FB pin to an internal reference voltage VFB of 1.0V (typical). The resistor values are calculated using:

Equation 2. V O U T ( m a x ) = V F B × R F B T + R F B B R F B B

RFBT is set to 100kΩ and RFBB is set to 1.87kΩ in this application.

6. EN/UVLO

The EN/UVLO pin provides dual functionality: device enable and undervoltage lockout (UVLO) protection. The internal logic and reference circuits activate once the pin voltage exceeds the enable threshold VT+(EN). The integrated UVLO circuit continuously monitors the input voltage; when it falls below the programmed threshold (8V for this application), the converter automatically shuts down to prevent damage to the power stage and LED load from low-voltage operation. The 8V UVLO threshold is established using a resistive divider network: RUV1 = 15.8kΩ (connected between VIN and EN/UVLO) and RUV2 = 2.94kΩ (connected between EN/UVLO and AGND). The resistor values can be determined using the LM51770-Q1 Calculation Tool or by referencing Section 8.3.5 (Enable and Undervoltage Lockout) in the device LM51770-Q1 datasheet.